Skip to content

Commit 0f7f6c0

Browse files
kamilrakoczykamilrakoczy
authored
Merge pull request chipsalliance#320 from antmicro/update-patch
Update patch
2 parents c3624d0 + 1da9116 commit 0f7f6c0

File tree

2 files changed

+64
-86
lines changed

2 files changed

+64
-86
lines changed

‎uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch‎

Lines changed: 63 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,12 @@
11
diff --git a/hw/ip/alert_handler/rtl/alert_handler.sv b/hw/ip/alert_handler/rtl/alert_handler.sv
2-
index 65035ad0b..40e915975 100644
2+
index 65035ad0b..001825885 100644
33
--- a/hw/ip/alert_handler/rtl/alert_handler.sv
44
+++ b/hw/ip/alert_handler/rtl/alert_handler.sv
5-
@@ -42,8 +42,8 @@ module alert_handler
6-
//////////////////////////////////
5+
@@ -43,7 +43,7 @@ module alert_handler
76

87
logic [N_CLASSES-1:0] irq;
9-
- hw2reg_wrap_t hw2reg_wrap;
8+
hw2reg_wrap_t hw2reg_wrap;
109
- reg2hw_wrap_t reg2hw_wrap;
11-
+ wire [220:0] hw2reg_wrap;
1210
+ wire [811:0] reg2hw_wrap;
1311

1412
// TODO: make this fully parametric at some point
@@ -35,44 +33,36 @@ index 65035ad0b..40e915975 100644
3533

3634
///////////////////////////////////////
3735
// Set alert cause bits and classify //
38-
@@ -125,13 +125,13 @@ module alert_handler
36+
@@ -125,10 +125,10 @@ module alert_handler
3937
alert_handler_class i_class (
4038
.alert_trig_i ( alert_trig ),
4139
.loc_alert_trig_i ( loc_alert_trig ),
4240
- .alert_en_i ( reg2hw_wrap.alert_en ),
4341
- .loc_alert_en_i ( reg2hw_wrap.loc_alert_en ),
4442
- .alert_class_i ( reg2hw_wrap.alert_class ),
4543
- .loc_alert_class_i ( reg2hw_wrap.loc_alert_class ),
46-
- .alert_cause_o ( hw2reg_wrap.alert_cause ),
47-
- .loc_alert_cause_o ( hw2reg_wrap.loc_alert_cause ),
48-
- .class_trig_o ( hw2reg_wrap.class_trig )
4944
+ .alert_en_i(reg2hw_wrap[774-:5]),
5045
+ .loc_alert_en_i(reg2hw_wrap[786-:4]),
5146
+ .alert_class_i(reg2hw_wrap[769-:10]),
5247
+ .loc_alert_class_i(reg2hw_wrap[782-:8]),
53-
+ .alert_cause_o(hw2reg_wrap[220-:5]),
54-
+ .loc_alert_cause_o(hw2reg_wrap[215-:4]),
55-
+ .class_trig_o(hw2reg_wrap[211-:4])
56-
);
57-
58-
////////////////////////////////////
59-
@@ -145,30 +145,30 @@ module alert_handler
48+
.alert_cause_o ( hw2reg_wrap.alert_cause ),
49+
.loc_alert_cause_o ( hw2reg_wrap.loc_alert_cause ),
50+
.class_trig_o ( hw2reg_wrap.class_trig )
51+
@@ -145,10 +145,10 @@ module alert_handler
6052
alert_handler_accu i_accu (
6153
.clk_i,
6254
.rst_ni,
6355
- .class_en_i ( reg2hw_wrap.class_en[k] ),
6456
- .clr_i ( reg2hw_wrap.class_clr[k] ),
65-
- .class_trig_i ( hw2reg_wrap.class_trig[k] ),
66-
- .thresh_i ( reg2hw_wrap.class_accum_thresh[k] ),
67-
- .accu_cnt_o ( hw2reg_wrap.class_accum_cnt[k] ),
6857
+ .class_en_i(reg2hw_wrap[756 + k]),
6958
+ .clr_i(reg2hw_wrap[752 + k]),
70-
+ .class_trig_i(hw2reg_wrap[208 + k]),
59+
.class_trig_i ( hw2reg_wrap.class_trig[k] ),
60+
- .thresh_i ( reg2hw_wrap.class_accum_thresh[k] ),
7161
+ .thresh_i(reg2hw_wrap[688 + (k * AccuCntDw)+:AccuCntDw]),
72-
+ .accu_cnt_o(hw2reg_wrap[140 + (k * AccuCntDw)+:AccuCntDw]),
62+
.accu_cnt_o ( hw2reg_wrap.class_accum_cnt[k] ),
7363
.accu_trig_o ( class_accum_trig[k] )
7464
);
75-
65+
@@ -156,16 +156,16 @@ module alert_handler
7666
alert_handler_esc_timer i_esc_timer (
7767
.clk_i,
7868
.rst_ni,
@@ -88,29 +78,20 @@ index 65035ad0b..40e915975 100644
8878
- .esc_en_i ( reg2hw_wrap.class_esc_en[k] ),
8979
- .esc_map_i ( reg2hw_wrap.class_esc_map[k] ),
9080
- .phase_cyc_i ( reg2hw_wrap.class_phase_cyc[k] ),
91-
- .esc_trig_o ( hw2reg_wrap.class_esc_trig[k] ),
92-
- .esc_cnt_o ( hw2reg_wrap.class_esc_cnt[k] ),
93-
- .esc_state_o ( hw2reg_wrap.class_esc_state[k] ),
9481
+ .timeout_cyc_i(reg2hw_wrap[560 + (k * EscCntDw)+:EscCntDw]),
9582
+ .esc_en_i(reg2hw_wrap[32 + (k * N_ESC_SEV)+:N_ESC_SEV]),
9683
+ .esc_map_i(reg2hw_wrap[k]),
9784
+ .phase_cyc_i(reg2hw_wrap[48 + k]),
98-
+ .esc_trig_o(hw2reg_wrap[204 + k]),
99-
+ .esc_cnt_o(hw2reg_wrap[12 + (k * EscCntDw)+:EscCntDw]),
100-
+ .esc_state_o(hw2reg_wrap[k * 3+:3]),
101-
.esc_sig_en_o ( class_esc_sig_en[k] )
102-
);
103-
end
85+
.esc_trig_o ( hw2reg_wrap.class_esc_trig[k] ),
86+
.esc_cnt_o ( hw2reg_wrap.class_esc_cnt[k] ),
87+
.esc_state_o ( hw2reg_wrap.class_esc_state[k] ),
10488
diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
105-
index f6dbddef4..bb30fe083 100644
89+
index f6dbddef4..0cbe62395 100644
10690
--- a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
10791
+++ b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
108-
@@ -15,9 +15,9 @@ module alert_handler_reg_wrap import alert_pkg::*; (
109-
// State information for HW crashdump
110-
output alert_crashdump_t crashdump_o,
92+
@@ -17,7 +17,7 @@ module alert_handler_reg_wrap import alert_pkg::*; (
11193
// hw2reg
112-
- input hw2reg_wrap_t hw2reg_wrap,
113-
+ input wire [220:0] hw2reg_wrap,
94+
input hw2reg_wrap_t hw2reg_wrap,
11495
// reg2hw
11596
- output reg2hw_wrap_t reg2hw_wrap
11697
+ output wire [811:0] reg2hw_wrap
@@ -133,15 +114,14 @@ index f6dbddef4..bb30fe083 100644
133114
prim_intr_hw #(
134115
.Width(1)
135116
- ) i_irq_classa (
136-
- .event_intr_i ( hw2reg_wrap.class_trig[0] ),
117+
+ ) i_irq_classa(
118+
.event_intr_i ( hw2reg_wrap.class_trig[0] ),
137119
- .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classa.q ),
138120
- .reg2hw_intr_test_q_i ( reg2hw.intr_test.classa.q ),
139121
- .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classa.qe ),
140122
- .reg2hw_intr_state_q_i ( reg2hw.intr_state.classa.q ),
141123
- .hw2reg_intr_state_de_o ( hw2reg.intr_state.classa.de ),
142124
- .hw2reg_intr_state_d_o ( hw2reg.intr_state.classa.d ),
143-
+ ) i_irq_classa(
144-
+ .event_intr_i ( hw2reg_wrap[208] ),
145125
+ .reg2hw_intr_enable_q_i ( reg2hw[840] ),
146126
+ .reg2hw_intr_test_q_i ( reg2hw[836] ),
147127
+ .reg2hw_intr_test_qe_i ( reg2hw[835] ),
@@ -154,15 +134,14 @@ index f6dbddef4..bb30fe083 100644
154134
prim_intr_hw #(
155135
.Width(1)
156136
- ) i_irq_classb (
157-
- .event_intr_i ( hw2reg_wrap.class_trig[1] ),
137+
+ ) i_irq_classb(
138+
.event_intr_i ( hw2reg_wrap.class_trig[1] ),
158139
- .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classb.q ),
159140
- .reg2hw_intr_test_q_i ( reg2hw.intr_test.classb.q ),
160141
- .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classb.qe ),
161142
- .reg2hw_intr_state_q_i ( reg2hw.intr_state.classb.q ),
162143
- .hw2reg_intr_state_de_o ( hw2reg.intr_state.classb.de ),
163144
- .hw2reg_intr_state_d_o ( hw2reg.intr_state.classb.d ),
164-
+ ) i_irq_classb(
165-
+ .event_intr_i ( hw2reg_wrap[209] ),
166145
+ .reg2hw_intr_enable_q_i ( reg2hw[839] ),
167146
+ .reg2hw_intr_test_q_i ( reg2hw[834] ),
168147
+ .reg2hw_intr_test_qe_i ( reg2hw[833] ),
@@ -175,15 +154,14 @@ index f6dbddef4..bb30fe083 100644
175154
prim_intr_hw #(
176155
.Width(1)
177156
- ) i_irq_classc (
178-
- .event_intr_i ( hw2reg_wrap.class_trig[2] ),
157+
+ ) i_irq_classc(
158+
.event_intr_i ( hw2reg_wrap.class_trig[2] ),
179159
- .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classc.q ),
180160
- .reg2hw_intr_test_q_i ( reg2hw.intr_test.classc.q ),
181161
- .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classc.qe ),
182162
- .reg2hw_intr_state_q_i ( reg2hw.intr_state.classc.q ),
183163
- .hw2reg_intr_state_de_o ( hw2reg.intr_state.classc.de ),
184164
- .hw2reg_intr_state_d_o ( hw2reg.intr_state.classc.d ),
185-
+ ) i_irq_classc(
186-
+ .event_intr_i ( hw2reg_wrap[210] ),
187165
+ .reg2hw_intr_enable_q_i ( reg2hw[838] ),
188166
+ .reg2hw_intr_test_q_i ( reg2hw[832] ),
189167
+ .reg2hw_intr_test_qe_i ( reg2hw[831] ),
@@ -196,15 +174,14 @@ index f6dbddef4..bb30fe083 100644
196174
prim_intr_hw #(
197175
.Width(1)
198176
- ) i_irq_classd (
199-
- .event_intr_i ( hw2reg_wrap.class_trig[3] ),
177+
+ ) i_irq_classd(
178+
.event_intr_i ( hw2reg_wrap.class_trig[3] ),
200179
- .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classd.q ),
201180
- .reg2hw_intr_test_q_i ( reg2hw.intr_test.classd.q ),
202181
- .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classd.qe ),
203182
- .reg2hw_intr_state_q_i ( reg2hw.intr_state.classd.q ),
204183
- .hw2reg_intr_state_de_o ( hw2reg.intr_state.classd.de ),
205184
- .hw2reg_intr_state_d_o ( hw2reg.intr_state.classd.d ),
206-
+ ) i_irq_classd(
207-
+ .event_intr_i ( hw2reg_wrap[211] ),
208185
+ .reg2hw_intr_enable_q_i ( reg2hw[837] ),
209186
+ .reg2hw_intr_test_q_i ( reg2hw[830] ),
210187
+ .reg2hw_intr_test_qe_i ( reg2hw[829] ),
@@ -214,25 +191,25 @@ index f6dbddef4..bb30fe083 100644
214191
.intr_o ( irq_o[3] )
215192
);
216193

217-
@@ -102,185 +102,62 @@ module alert_handler_reg_wrap import alert_pkg::*; (
194+
@@ -102,185 +102,80 @@ module alert_handler_reg_wrap import alert_pkg::*; (
218195
// if an alert is enabled and it fires,
219196
// we have to set the corresponding cause bit
220197
for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause
221198
- assign hw2reg.alert_cause[k].d = 1'b1;
222199
- assign hw2reg.alert_cause[k].de = reg2hw.alert_cause[k].q |
223-
- hw2reg_wrap.alert_cause[k];
224200
+ assign hw2reg[220 + ((k * 2) + 1)] = 1'b1;
225-
+ assign hw2reg[220 + (k * 2)] = reg2hw[784 + k] | hw2reg_wrap[216 + k];
201+
+ assign hw2reg[220 + (k * 2)] = reg2hw[784 + k] |
202+
hw2reg_wrap.alert_cause[k];
226203
end
227204

228205
// if a local alert is enabled and it fires,
229206
// we have to set the corresponding cause bit
230207
for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause
231208
- assign hw2reg.loc_alert_cause[k].d = 1'b1;
232209
- assign hw2reg.loc_alert_cause[k].de = reg2hw.loc_alert_cause[k].q |
233-
- hw2reg_wrap.loc_alert_cause[k];
234210
+ assign hw2reg[212 + ((k * 2) + 1)] = 1'b1;
235-
+ assign hw2reg[212 + (k * 2)] = reg2hw[768 + k] | hw2reg_wrap[212 + k];
211+
+ assign hw2reg[212 + (k * 2)] = reg2hw[768 + k] |
212+
hw2reg_wrap.loc_alert_cause[k];
236213
end
237214

238215
// ping timeout in cycles
@@ -249,39 +226,48 @@ index f6dbddef4..bb30fe083 100644
249226
- hw2reg.classa_clren.de } = hw2reg_wrap.class_esc_trig &
250227
- class_autolock_en &
251228
- reg2hw_wrap.class_en;
252-
-
253-
- // current accumulator counts
229+
+ assign { hw2reg[52],
230+
+ hw2reg[105],
231+
+ hw2reg[158],
232+
+ hw2reg[211] } = '0;
233+
+
234+
+ assign { hw2reg[51],
235+
+ hw2reg[104],
236+
+ hw2reg[157],
237+
+ hw2reg[210] } = hw2reg_wrap.class_esc_trig &
238+
+ class_autolock_en &
239+
+ reg2hw_wrap[759-:4];
240+
241+
// current accumulator counts
254242
- assign { hw2reg.classd_accum_cnt.d,
255243
- hw2reg.classc_accum_cnt.d,
256244
- hw2reg.classb_accum_cnt.d,
257245
- hw2reg.classa_accum_cnt.d } = hw2reg_wrap.class_accum_cnt;
258-
-
259-
- // current accumulator counts
246+
+ assign { hw2reg[209-:16],
247+
+ hw2reg[156-:16],
248+
+ hw2reg[103-:16],
249+
+ hw2reg[50-:16] } = hw2reg_wrap.class_accum_cnt;
250+
251+
// current accumulator counts
260252
- assign { hw2reg.classd_esc_cnt.d,
261253
- hw2reg.classc_esc_cnt.d,
262254
- hw2reg.classb_esc_cnt.d,
263255
- hw2reg.classa_esc_cnt.d } = hw2reg_wrap.class_esc_cnt;
264-
-
265-
- // current accumulator counts
256+
+ assign { hw2reg[193-:32],
257+
+ hw2reg[140-:32],
258+
+ hw2reg[87-:32],
259+
+ hw2reg[34-:32] } = hw2reg_wrap.class_esc_cnt;
260+
261+
// current accumulator counts
266262
- assign { hw2reg.classd_state.d,
267263
- hw2reg.classc_state.d,
268264
- hw2reg.classb_state.d,
269265
- hw2reg.classa_state.d } = hw2reg_wrap.class_esc_state;
270-
-
271-
+ assign {hw2reg[52], hw2reg[105], hw2reg[158], hw2reg[211]} = {4 {1'b0}};
272-
+ assign {hw2reg[51], hw2reg[104], hw2reg[157], hw2reg[210]} = (hw2reg_wrap[207-:4] & class_autolock_en) & reg2hw_wrap[759-:4];
273-
+ assign hw2reg[209-:16] = hw2reg_wrap[203-:16];
274-
+ assign hw2reg[156-:16] = hw2reg_wrap[187-:16];
275-
+ assign hw2reg[103-:16] = hw2reg_wrap[171-:16];
276-
+ assign hw2reg[50-:16] = hw2reg_wrap[155-:16];
277-
+ assign hw2reg[193-:32] = hw2reg_wrap[139-:32];
278-
+ assign hw2reg[140-:32] = hw2reg_wrap[107-:32];
279-
+ assign hw2reg[87-:32] = hw2reg_wrap[75-:32];
280-
+ assign hw2reg[34-:32] = hw2reg_wrap[43-:32];
281-
+ assign hw2reg[161-:3] = hw2reg_wrap[11-:3];
282-
+ assign hw2reg[108-:3] = hw2reg_wrap[8-:3];
283-
+ assign hw2reg[55-:3] = hw2reg_wrap[5-:3];
284-
+ assign hw2reg[2-:3] = hw2reg_wrap[2-:3];
266+
+ assign { hw2reg[161-:3],
267+
+ hw2reg[108-:3],
268+
+ hw2reg[55-:3],
269+
+ hw2reg[2-:3] } = hw2reg_wrap.class_esc_state;
270+
285271
/////////////////////
286272
// reg2hw mappings //
287273
/////////////////////
@@ -432,7 +418,7 @@ index f6dbddef4..bb30fe083 100644
432418

433419
//////////////////////
434420
// crashdump output //
435-
@@ -288,17 +165,17 @@ module alert_handler_reg_wrap import alert_pkg::*; (
421+
@@ -288,12 +183,12 @@ module alert_handler_reg_wrap import alert_pkg::*; (
436422

437423
// alert cause output
438424
for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause_dump
@@ -446,15 +432,7 @@ index f6dbddef4..bb30fe083 100644
446432
+ assign crashdump_o.loc_alert_cause[k] = reg2hw[768 + k];
447433
end
448434

449-
- assign crashdump_o.class_accum_cnt = hw2reg_wrap.class_accum_cnt;
450-
- assign crashdump_o.class_esc_cnt = hw2reg_wrap.class_esc_cnt;
451-
- assign crashdump_o.class_esc_state = hw2reg_wrap.class_esc_state;
452-
+ assign crashdump_o.class_accum_cnt = hw2reg_wrap[203-:64];
453-
+ assign crashdump_o.class_esc_cnt = hw2reg_wrap[139-:128];
454-
+ assign crashdump_o.class_esc_state = hw2reg_wrap[11-:12];
455-
456-
endmodule : alert_handler_reg_wrap
457-
435+
assign crashdump_o.class_accum_cnt = hw2reg_wrap.class_accum_cnt;
458436
diff --git a/hw/ip/alert_handler/rtl/alert_pkg.sv b/hw/ip/alert_handler/rtl/alert_pkg.sv
459437
index 5324b4978..a1a858232 100644
460438
--- a/hw/ip/alert_handler/rtl/alert_pkg.sv

‎yosys-symbiflow-plugins‎

0 commit comments

Comments
 (0)