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Merge pull request chipsalliance#359 from antmicro/bump-surelog
Bump surelog
2 parents 2a37a68 + 273bfff commit 345ab77

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Surelog

Submodule Surelog updated 56 files

uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch

Lines changed: 0 additions & 151 deletions
Original file line numberDiff line numberDiff line change
@@ -522,157 +522,6 @@ index 962d3b559..9d5a10c8c 100644
522522
`endif
523523
end
524524

525-
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
526-
index 2acc14e86..692284ba3 100644
527-
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
528-
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
529-
@@ -239,8 +239,8 @@ module top_earlgrey #(
530-
assign unused_irq_id = irq_id;
531-
532-
// Alert list
533-
- prim_alert_pkg::alert_tx_t [alert_pkg::NAlerts-1:0] alert_tx;
534-
- prim_alert_pkg::alert_rx_t [alert_pkg::NAlerts-1:0] alert_rx;
535-
+ wire [9:0] alert_tx;
536-
+ wire [19:0] alert_rx;
537-
// Escalation outputs
538-
prim_esc_pkg::esc_tx_t [alert_pkg::N_ESC_SEV-1:0] esc_tx;
539-
prim_esc_pkg::esc_rx_t [alert_pkg::N_ESC_SEV-1:0] esc_rx;
540-
@@ -259,12 +259,12 @@ module top_earlgrey #(
541-
pwrmgr_pkg::pwr_cpu_t pwrmgr_pwr_cpu;
542-
clkmgr_pkg::clkmgr_out_t clkmgr_clocks;
543-
logic aes_idle;
544-
- clkmgr_pkg::clk_hint_status_t clkmgr_status;
545-
+ reg [2:0] clkmgr_status;
546-
547-
always_comb begin
548-
// TODO: So far just aes is connected
549-
- clkmgr_status.idle = clkmgr_pkg::CLK_HINT_STATUS_DEFAULT;
550-
- clkmgr_status.idle[0] = aes_idle;
551-
+ clkmgr_status[2-:3] = clkmgr_pkg::CLK_HINT_STATUS_DEFAULT;
552-
+ clkmgr_status[0] = aes_idle;
553-
end
554-
555-
// Non-debug module reset == reset for everything except for the debug module
556-
@@ -612,6 +612,8 @@ module top_earlgrey #(
557-
.rst_ni (rstmgr_resets.rst_spi_device_n)
558-
);
559-
560-
+ import flash_ctrl_pkg::*;
561-
+
562-
flash_ctrl u_flash_ctrl (
563-
.tl_i (tl_flash_ctrl_d_h2d),
564-
.tl_o (tl_flash_ctrl_d_d2h),
565-
@@ -627,7 +629,7 @@ module top_earlgrey #(
566-
// Inter-module signals
567-
.flash_o(flash_ctrl_flash_req),
568-
.flash_i(flash_ctrl_flash_rsp),
569-
- .otp_i(flash_ctrl_pkg::OTP_FLASH_DEFAULT),
570-
+ .otp_i(OTP_FLASH_DEFAULT),
571-
.clk_i (clkmgr_clocks.clk_main_infra),
572-
.rst_ni (rstmgr_resets.rst_lc_n)
573-
);
574-
@@ -647,8 +649,8 @@ module top_earlgrey #(
575-
.tl_o (tl_aes_d_d2h),
576-
577-
// [0]: ctrl_err
578-
- .alert_tx_o ( alert_tx[0:0] ),
579-
- .alert_rx_i ( alert_rx[0:0] ),
580-
+ .alert_tx_o ( alert_tx[0+:2] ),
581-
+ .alert_rx_i ( alert_rx[0+:4] ),
582-
583-
// Inter-module signals
584-
.idle_o(aes_idle),
585-
@@ -666,8 +668,8 @@ module top_earlgrey #(
586-
.intr_hmac_err_o (intr_hmac_hmac_err),
587-
588-
// [1]: msg_push_sha_disabled
589-
- .alert_tx_o ( alert_tx[1:1] ),
590-
- .alert_rx_i ( alert_rx[1:1] ),
591-
+ .alert_tx_o ( alert_tx[2+:2] ),
592-
+ .alert_rx_i ( alert_rx[4+:4] ),
593-
.clk_i (clkmgr_clocks.clk_main_hmac),
594-
.rst_ni (rstmgr_resets.rst_sys_n)
595-
);
596-
@@ -750,6 +752,8 @@ module top_earlgrey #(
597-
.rst_ni (rstmgr_resets.rst_sys_n)
598-
);
599-
600-
+ import pwrmgr_pkg::*;
601-
+
602-
pwrmgr u_pwrmgr (
603-
.tl_i (tl_pwrmgr_d_h2d),
604-
.tl_o (tl_pwrmgr_d_d2h),
605-
@@ -759,16 +763,16 @@ module top_earlgrey #(
606-
607-
// Inter-module signals
608-
.pwr_ast_o(),
609-
- .pwr_ast_i(pwrmgr_pkg::PWR_AST_RSP_DEFAULT),
610-
+ .pwr_ast_i(PWR_AST_RSP_DEFAULT),
611-
.pwr_rst_o(pwrmgr_pwr_rst_req),
612-
.pwr_rst_i(pwrmgr_pwr_rst_rsp),
613-
.pwr_clk_o(pwrmgr_pwr_clk_req),
614-
.pwr_clk_i(pwrmgr_pwr_clk_rsp),
615-
.pwr_otp_o(),
616-
- .pwr_otp_i(pwrmgr_pkg::PWR_OTP_RSP_DEFAULT),
617-
+ .pwr_otp_i(PWR_OTP_RSP_DEFAULT),
618-
.pwr_lc_o(),
619-
- .pwr_lc_i(pwrmgr_pkg::PWR_LC_RSP_DEFAULT),
620-
- .pwr_flash_i(pwrmgr_pkg::PWR_FLASH_DEFAULT),
621-
+ .pwr_lc_i(PWR_LC_RSP_DEFAULT),
622-
+ .pwr_flash_i(PWR_FLASH_DEFAULT),
623-
.pwr_cpu_i(pwrmgr_pwr_cpu),
624-
.wakeups_i(pwrmgr_wakeups),
625-
.rstreqs_i('0),
626-
@@ -778,6 +782,8 @@ module top_earlgrey #(
627-
.rst_slow_ni (rstmgr_resets.rst_por_aon_n)
628-
);
629-
630-
+ import rstmgr_pkg::*;
631-
+
632-
rstmgr u_rstmgr (
633-
.tl_i (tl_rstmgr_d_h2d),
634-
.tl_o (tl_rstmgr_d_d2h),
635-
@@ -786,9 +792,9 @@ module top_earlgrey #(
636-
.pwr_i(pwrmgr_pwr_rst_req),
637-
.pwr_o(pwrmgr_pwr_rst_rsp),
638-
.resets_o(rstmgr_resets),
639-
- .ast_i(rstmgr_pkg::RSTMGR_AST_DEFAULT),
640-
+ .ast_i(RSTMGR_AST_DEFAULT),
641-
.cpu_i(rstmgr_cpu),
642-
- .peri_i(rstmgr_pkg::RSTMGR_PERI_DEFAULT),
643-
+ .peri_i(RSTMGR_PERI_DEFAULT),
644-
.scanmode_i (scanmode_i),
645-
.scan_rst_ni (scan_rst_ni),
646-
.clk_i (clkmgr_clocks.clk_io_powerup),
647-
@@ -800,6 +806,8 @@ module top_earlgrey #(
648-
.rst_ni (rst_ni)
649-
);
650-
651-
+ import clkmgr_pkg::*;
652-
+
653-
clkmgr u_clkmgr (
654-
.tl_i (tl_clkmgr_d_h2d),
655-
.tl_o (tl_clkmgr_d_d2h),
656-
@@ -812,7 +820,7 @@ module top_earlgrey #(
657-
.clk_aon_i(clkmgr_clk_aon),
658-
.pwr_i(pwrmgr_pwr_clk_req),
659-
.pwr_o(pwrmgr_pwr_clk_rsp),
660-
- .dft_i(clkmgr_pkg::CLK_DFT_DEFAULT),
661-
+ .dft_i(CLK_DFT_DEFAULT),
662-
.status_i(clkmgr_status),
663-
.clk_i (clkmgr_clocks.clk_io_powerup),
664-
.rst_ni (rstmgr_resets.rst_por_io_n),
665-
@@ -904,8 +912,8 @@ module top_earlgrey #(
666-
// [2]: imem_uncorrectable
667-
// [3]: dmem_uncorrectable
668-
// [4]: reg_uncorrectable
669-
- .alert_tx_o ( alert_tx[4:2] ),
670-
- .alert_rx_i ( alert_rx[4:2] ),
671-
+ .alert_tx_o ( alert_tx[4+:6] ),
672-
+ .alert_rx_i ( alert_rx[8+:12] ),
673-
674-
// Inter-module signals
675-
.idle_o(),
676525
diff --git a/hw/top_earlgrey/top_earlgrey_nexysvideo.core b/hw/top_earlgrey/top_earlgrey_nexysvideo.core
677526
index 8d6cf89b6..1683f0693 100644
678527
--- a/hw/top_earlgrey/top_earlgrey_nexysvideo.core

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