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kamilrakoczykamilrakoczy
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Merge pull request chipsalliance#352 from antmicro/ibex
Bump ibex
2 parents d33a23f + b2a29c2 commit f5627be

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‎uhdm-tests/ibex/ibex‎

Submodule ibex updated 457 files

‎uhdm-tests/ibex/top_artya7_core.patch‎

Lines changed: 54 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -1,101 +1,8 @@
1-
From e9601e43c6a07014a29f90d9f747f4abe0f1fb9b Mon Sep 17 00:00:00 2001
2-
From: Kamil Rakoczy <[email protected]>
3-
Date: Thu, 23 Dec 2021 12:57:35 +0100
4-
Subject: [PATCH 2/3] add synth surelog target
5-
6-
Signed-off-by: Kamil Rakoczy <[email protected]>
7-
---
8-
examples/fpga/artya7/top_artya7.core | 25 ++++++++++++++++++++++---
9-
1 file changed, 22 insertions(+), 3 deletions(-)
10-
11-
diff --git a/examples/fpga/artya7/top_artya7.core b/examples/fpga/artya7/top_artya7.core
12-
index 4493a8ae..9a5e538b 100644
13-
--- a/examples/fpga/artya7/top_artya7.core
14-
+++ b/examples/fpga/artya7/top_artya7.core
15-
@@ -2,7 +2,7 @@ CAPI=2:
16-
# Copyright lowRISC contributors.
17-
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
18-
# SPDX-License-Identifier: Apache-2.0
19-
-name: "lowrisc:ibex:top_artya7:0.1"
20-
+name: "lowrisc:ibex:top_artya7_surelog:0.1"
21-
description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)"
22-
filesets:
23-
files_rtl_artya7:
24-
@@ -17,6 +17,10 @@ filesets:
25-
files:
26-
- data/pins_artya7.xdc
27-
file_type: xdc
28-
+ files_constraints_sdc:
29-
+ files:
30-
+ - data/pins_artya7.sdc
31-
+ file_type: SDC
32-
33-
files_tcl:
34-
files:
35-
@@ -41,7 +45,7 @@ parameters:
36-
datatype: str
37-
paramtype: vlogdefine
38-
description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
39-
-
40-
+
41-
FPGAPowerAnalysis:
42-
datatype: int
43-
paramtype: vlogparam
44-
@@ -53,7 +57,7 @@ targets:
45-
filesets:
46-
- files_rtl_artya7
47-
- files_constraints
48-
- - files_tcl
49-
+ - tool_symbiflow ? (files_constraints_sdc)
50-
toplevel: top_artya7
51-
parameters:
52-
- SRAMInitFile
53-
@@ -62,3 +66,18 @@ targets:
54-
tools:
55-
vivado:
56-
part: "xc7a100tcsg324-1" # Default to Arty A7-100
57-
+ synth: "yosys"
58-
+ yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"]
59-
+ yosys_read_options: ['-noassert', '-debug']
60-
+ surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
61-
+ yosys:
62-
+ arch: "xilinx"
63-
+ yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"]
64-
+ yosys_read_options: ['-noassert']
65-
+ surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
66-
+ symbiflow:
67-
+ package: "csg324-1"
68-
+ part: "xc7a35t"
69-
+ pnr: "vtr"
70-
+ vendor: "xilinx"
71-
+ surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
72-
--
73-
2.33.1
74-
75-
From 7b0e214fcb86aac8331da89f378ba0dbccc4f0d3 Mon Sep 17 00:00:00 2001
76-
From: Kamil Rakoczy <[email protected]>
77-
Date: Thu, 23 Dec 2021 12:58:11 +0100
78-
Subject: [PATCH 3/3] ibex: change ram_2p to ram_1p
79-
80-
---
81-
examples/fpga/artya7/rtl/top_artya7.sv | 46 +++++++++++++++-----------
82-
shared/fpga_xilinx.core | 4 +--
83-
2 files changed, 28 insertions(+), 22 deletions(-)
84-
851
diff --git a/examples/fpga/artya7/rtl/top_artya7.sv b/examples/fpga/artya7/rtl/top_artya7.sv
86-
index 5efbf270..e91db9fd 100644
2+
index b15ee978..7ed562bb 100644
873
--- a/examples/fpga/artya7/rtl/top_artya7.sv
884
+++ b/examples/fpga/artya7/rtl/top_artya7.sv
89-
@@ -8,7 +8,7 @@ module top_artya7 (
90-
output [3:0] LED
91-
);
92-
93-
- parameter int MEM_SIZE = 256 * 1024; // 256 kB
94-
+ parameter int MEM_SIZE = 32 * 1024; // 32 kB
95-
parameter logic [31:0] MEM_START = 32'h00000000;
96-
parameter logic [31:0] MEM_MASK = MEM_SIZE-1;
97-
parameter SRAMInitFile = "";
98-
@@ -84,28 +84,34 @@ module top_artya7 (
5+
@@ -87,28 +87,34 @@ module top_artya7 (
996
);
1007

1018
// SRAM block for instruction and data storage
@@ -148,7 +55,59 @@ index 5efbf270..e91db9fd 100644
14855
+ .rdata_o ( instr_rdata )
14956
);
15057

58+
assign instr_gnt = instr_req;
59+
diff --git a/examples/fpga/artya7/top_artya7.core b/examples/fpga/artya7/top_artya7.core
60+
index 4493a8ae..bbe9c6c8 100644
61+
--- a/examples/fpga/artya7/top_artya7.core
62+
+++ b/examples/fpga/artya7/top_artya7.core
63+
@@ -2,7 +2,7 @@ CAPI=2:
64+
# Copyright lowRISC contributors.
65+
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
66+
# SPDX-License-Identifier: Apache-2.0
67+
-name: "lowrisc:ibex:top_artya7:0.1"
68+
+name: "lowrisc:ibex:top_artya7_surelog:0.1"
69+
description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)"
70+
filesets:
71+
files_rtl_artya7:
72+
@@ -17,6 +17,10 @@ filesets:
73+
files:
74+
- data/pins_artya7.xdc
75+
file_type: xdc
76+
+ files_constraints_sdc:
77+
+ files:
78+
+ - data/pins_artya7.sdc
79+
+ file_type: SDC
15180

81+
files_tcl:
82+
files:
83+
@@ -53,7 +57,7 @@ targets:
84+
filesets:
85+
- files_rtl_artya7
86+
- files_constraints
87+
- - files_tcl
88+
+ - tool_symbiflow ? (files_constraints_sdc)
89+
toplevel: top_artya7
90+
parameters:
91+
- SRAMInitFile
92+
@@ -62,3 +66,18 @@ targets:
93+
tools:
94+
vivado:
95+
part: "xc7a100tcsg324-1" # Default to Arty A7-100
96+
+ synth: "yosys"
97+
+ yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"]
98+
+ yosys_read_options: ['-debug']
99+
+ surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
100+
+ yosys:
101+
+ arch: "xilinx"
102+
+ yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"]
103+
+ yosys_read_options: ['-debug']
104+
+ surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
105+
+ symbiflow:
106+
+ package: "csg324-1"
107+
+ part: "xc7a35t"
108+
+ pnr: "vtr"
109+
+ vendor: "xilinx"
110+
+ surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS']
152111
diff --git a/shared/fpga_xilinx.core b/shared/fpga_xilinx.core
153112
index 242f1f2d..26b05f1f 100644
154113
--- a/shared/fpga_xilinx.core
@@ -166,6 +125,3 @@ index 242f1f2d..26b05f1f 100644
166125
file_type: systemVerilogSource
167126

168127
targets:
169-
--
170-
2.33.1
171-

‎uhdm-tests/opentitan/0001-Add-opentitan-patch-for-uhdm.patch‎

Lines changed: 21 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -523,7 +523,7 @@ index 962d3b559..9d5a10c8c 100644
523523
end
524524

525525
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
526-
index 2acc14e86..c6aa89066 100644
526+
index 2acc14e86..692284ba3 100644
527527
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
528528
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
529529
@@ -239,8 +239,8 @@ module top_earlgrey #(
@@ -553,16 +553,25 @@ index 2acc14e86..c6aa89066 100644
553553
end
554554

555555
// Non-debug module reset == reset for everything except for the debug module
556-
@@ -627,7 +627,7 @@ module top_earlgrey #(
556+
@@ -612,6 +612,8 @@ module top_earlgrey #(
557+
.rst_ni (rstmgr_resets.rst_spi_device_n)
558+
);
559+
560+
+ import flash_ctrl_pkg::*;
561+
+
562+
flash_ctrl u_flash_ctrl (
563+
.tl_i (tl_flash_ctrl_d_h2d),
564+
.tl_o (tl_flash_ctrl_d_d2h),
565+
@@ -627,7 +629,7 @@ module top_earlgrey #(
557566
// Inter-module signals
558567
.flash_o(flash_ctrl_flash_req),
559568
.flash_i(flash_ctrl_flash_rsp),
560569
- .otp_i(flash_ctrl_pkg::OTP_FLASH_DEFAULT),
561-
+ .otp_i(256'hdeadbeefbeeffacedeadbeef5a5aa5a5deadbeef5a5aa5a5deadbeefbeefface),
570+
+ .otp_i(OTP_FLASH_DEFAULT),
562571
.clk_i (clkmgr_clocks.clk_main_infra),
563572
.rst_ni (rstmgr_resets.rst_lc_n)
564573
);
565-
@@ -647,8 +647,8 @@ module top_earlgrey #(
574+
@@ -647,8 +649,8 @@ module top_earlgrey #(
566575
.tl_o (tl_aes_d_d2h),
567576

568577
// [0]: ctrl_err
@@ -573,7 +582,7 @@ index 2acc14e86..c6aa89066 100644
573582

574583
// Inter-module signals
575584
.idle_o(aes_idle),
576-
@@ -666,8 +666,8 @@ module top_earlgrey #(
585+
@@ -666,8 +668,8 @@ module top_earlgrey #(
577586
.intr_hmac_err_o (intr_hmac_hmac_err),
578587

579588
// [1]: msg_push_sha_disabled
@@ -584,7 +593,7 @@ index 2acc14e86..c6aa89066 100644
584593
.clk_i (clkmgr_clocks.clk_main_hmac),
585594
.rst_ni (rstmgr_resets.rst_sys_n)
586595
);
587-
@@ -750,6 +750,8 @@ module top_earlgrey #(
596+
@@ -750,6 +752,8 @@ module top_earlgrey #(
588597
.rst_ni (rstmgr_resets.rst_sys_n)
589598
);
590599

@@ -593,7 +602,7 @@ index 2acc14e86..c6aa89066 100644
593602
pwrmgr u_pwrmgr (
594603
.tl_i (tl_pwrmgr_d_h2d),
595604
.tl_o (tl_pwrmgr_d_d2h),
596-
@@ -759,16 +761,16 @@ module top_earlgrey #(
605+
@@ -759,16 +763,16 @@ module top_earlgrey #(
597606

598607
// Inter-module signals
599608
.pwr_ast_o(),
@@ -614,7 +623,7 @@ index 2acc14e86..c6aa89066 100644
614623
.pwr_cpu_i(pwrmgr_pwr_cpu),
615624
.wakeups_i(pwrmgr_wakeups),
616625
.rstreqs_i('0),
617-
@@ -778,6 +780,8 @@ module top_earlgrey #(
626+
@@ -778,6 +782,8 @@ module top_earlgrey #(
618627
.rst_slow_ni (rstmgr_resets.rst_por_aon_n)
619628
);
620629

@@ -623,7 +632,7 @@ index 2acc14e86..c6aa89066 100644
623632
rstmgr u_rstmgr (
624633
.tl_i (tl_rstmgr_d_h2d),
625634
.tl_o (tl_rstmgr_d_d2h),
626-
@@ -786,9 +790,9 @@ module top_earlgrey #(
635+
@@ -786,9 +792,9 @@ module top_earlgrey #(
627636
.pwr_i(pwrmgr_pwr_rst_req),
628637
.pwr_o(pwrmgr_pwr_rst_rsp),
629638
.resets_o(rstmgr_resets),
@@ -635,7 +644,7 @@ index 2acc14e86..c6aa89066 100644
635644
.scanmode_i (scanmode_i),
636645
.scan_rst_ni (scan_rst_ni),
637646
.clk_i (clkmgr_clocks.clk_io_powerup),
638-
@@ -800,6 +804,8 @@ module top_earlgrey #(
647+
@@ -800,6 +806,8 @@ module top_earlgrey #(
639648
.rst_ni (rst_ni)
640649
);
641650

@@ -644,7 +653,7 @@ index 2acc14e86..c6aa89066 100644
644653
clkmgr u_clkmgr (
645654
.tl_i (tl_clkmgr_d_h2d),
646655
.tl_o (tl_clkmgr_d_d2h),
647-
@@ -812,7 +818,7 @@ module top_earlgrey #(
656+
@@ -812,7 +820,7 @@ module top_earlgrey #(
648657
.clk_aon_i(clkmgr_clk_aon),
649658
.pwr_i(pwrmgr_pwr_clk_req),
650659
.pwr_o(pwrmgr_pwr_clk_rsp),
@@ -653,7 +662,7 @@ index 2acc14e86..c6aa89066 100644
653662
.status_i(clkmgr_status),
654663
.clk_i (clkmgr_clocks.clk_io_powerup),
655664
.rst_ni (rstmgr_resets.rst_por_io_n),
656-
@@ -904,8 +910,8 @@ module top_earlgrey #(
665+
@@ -904,8 +912,8 @@ module top_earlgrey #(
657666
// [2]: imem_uncorrectable
658667
// [3]: dmem_uncorrectable
659668
// [4]: reg_uncorrectable

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