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[VL] Do not rewriteAggBufferAttributes for Complete agg mode #11358

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rui-mo merged 1 commit into from
Jan 14, 2026
Merged

[VL] Do not rewriteAggBufferAttributes for Complete agg mode #11358

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4 changes: 2 additions & 2 deletions backends-velox/src/main/scala/org/apache/gluten/execution/HashAggregateExecTransformer.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -284,7 +284,7 @@ abstract class HashAggregateExecTransformer(
val aggFunc = aggregateExpression.aggregateFunction
val functionInputAttributes = aggFunc.inputAggBufferAttributes
aggFunc match {
case _ if aggregateExpression.mode == Partial =>
case _ if aggregateExpression.mode == Partial || aggregateExpression.mode == Complete =>
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@rui-mo rui-mo Jan 13, 2026

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I understand that mixing Complete mode with other modes isn’t supported, but is there a way to add a unit test for pure Complete mode to ensure this works?

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@Zouxxyy Zouxxyy Jan 13, 2026

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We already have pure complete mode case, see #7752, and it can run correctly

val childNodes = aggFunc.children
.map(
ExpressionConverter
Expand All @@ -303,7 +303,7 @@ abstract class HashAggregateExecTransformer(
// The process of handling the inconsistency in column types and order between
// Spark and Velox is exactly the opposite of applyExtractStruct.
aggregateExpression.mode match {
case PartialMerge | Final | Complete =>
case PartialMerge | Final =>
val newInputAttributes = new ArrayBuffer[Attribute]()
val childNodes = new JArrayList[ExpressionNode]()
val (sparkOrders, sparkTypes) =
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