arch/risc-v/eic7700x: Add support for ESWIN EIC7700X SoC

[lupyuen]

Summary

This PR adds support for the ESWIN EIC7700X RISC-V SoC. This will be used by the upcoming port of NuttX for PINE64 StarPro64 SBC.

Most of the code was derived from NuttX for SOPHGO SG2000 SoC. The modified code is explained here

Modified Files in arch/risc-v

Kconfig: Added ARCH_CHIP_EIC7700X for EIC7700X SoC

New Files in arch/risc-v

include/eic7700x/chip.h: EIC7700X Definitions

include/eic7700x/irq.h: External Interrupts

src/eic7700x/chip.h: Interrupt Stack Macro

src/eic7700x/eic7700x_allocateheap.c: Kernel Heap

src/eic7700x/eic7700x_head.S: Linux Header and Boot Code

src/eic7700x/eic7700x_irq.c: Configure Interrupts

src/eic7700x/eic7700x_irq_dispatch.c: Dispatch Interrupts

src/eic7700x/eic7700x_memorymap.h: Memory Map

src/eic7700x/eic7700x_mm_init.c, eic7700x_mm_init.h: Memory Mgmt

src/eic7700x/eic7700x_pgalloc.c: Page Allocator

src/eic7700x/eic7700x_start.c: Startup Code

src/eic7700x/eic7700x_timerisr.c: Timer Interrupt

src/eic7700x/hardware/eic7700x_memorymap.h: PLIC and UART Base Address

src/eic7700x/hardware/eic7700x_plic.h: PLIC Register Addresses

src/eic7700x/Kconfig: EIC7700X Config

src/eic7700x/Make.defs: Makefile

Documentation

platforms/risc-v/eic7700x/index.rst: Added EIC7700X SoC

Impact

This PR is needed for the upcoming port of NuttX for PINE64 StarPro64 SBC.

No impact on existing code, since the EIC7700X source files are not used by existing code.

Testing

We tested the EIC7700X source files on PINE64 StarPro64 SBC. NuttX boots correctly to NSH Shell and passes OSTest:

• Board Source Code for StarPro64
• NuttX Log for StarPro64
• Build Log for StarPro64

NuttShell (NSH) NuttX-12.8.0
nsh> uname -a
NuttX 12.8.0 f81a1ae9ef Mar  3 2025 06:32:03 risc-v starpro64

nsh> free
      total       used       free    maxused    maxfree  nused  nfree name
    2057216      11632    2045584      33320    2042800     38      6 Kmem
   20971520     720896   20250624              20250624               Page

nsh> ls -l /dev
/dev:
 crw-rw-rw-           0 console
 crw-rw-rw-           0 null
 brw-rw-rw-    16777216 ram0
 crw-rw-rw-           0 ttyS0
 crw-rw-rw-           0 zero

nsh> ps
  PID GROUP PRI POLICY   TYPE    NPX STATE    EVENT     SIGMASK            STACK    USED FILLED COMMAND
    0     0   0 FIFO     Kthread   - Ready              0000000000000000 0003056 0001040  34.0%  Idle_Task
    1     0 100 RR       Kthread   - Waiting  Semaphore 0000000000000000 0001968 0000720  36.5%  lpwork 0x80400100 0x80400148
    3     3 100 RR       Task      - Running            0000000000000000 0003008 0001872  62.2%  /system/bin/init

nsh> hello
Hello, World!!

nsh> getprime
Set thread priority to 10
Set thread policy to SCHED_RR
Start thread #0
thread #0 started, looking for primes < 10000, doing 10 run(s)
thread #0 finished, found 1230 primes, last one was 9973
Done
getprime took 134 msec

nsh> ostest
...
Final memory usage:
VARIABLE  BEFORE   AFTER
======== ======== ========
arena       81000    81000
ordblks         2        3
mxordblk    7cff8    78ff8
uordblks     2660     4570
fordblks    7e9a0    7ca90
user_main: Exiting
ostest_main: Exiting with status 0

[nuttxpr]

[Experimental Bot, please feedback here]

Yes, this PR meets the NuttX requirements. The summary clearly explains the change, its purpose, and the affected files. The impact section adequately addresses the scope of the changes and confirms no impact on existing users, build processes, or other hardware. The testing section provides sufficient evidence of successful testing on the target hardware, including boot logs and the output of key commands like uname, free, ls, ps, hello, getprime, and ostest. The links to the board source code and build log are also helpful. The documentation update is mentioned, which is important. Overall, it's a well-structured and informative PR description.

[cederom]

Thank you @lupyuen Amazing Work!! =)

[hartmannathan]

Thanks for adding new arch support! Commit logs look good. Code is well-commented. I don't have this hardware to verify actual code but looks good on code reading.

[cederom]

Maybe we should mark this change with [EXPERIMENTAL] tag? Its the initial code and will be probably changed often? :-)

[lupyuen]

Actually the typos we found above are also present in other RISC-V ports: QEMU, SG2000, BL808, K230, MPFS, ... So it's not an "Experimental" issue, more like a "Legacy" fix that needs backporting 😬

Update: I found 20 source files with the same typos, I submitted the PR here:

• arch/arm, risc-v: Fix typos in Code Comments #15922

[acassis]

Nice work Lup!!!

[lupyuen]

Sorry @hartmannathan: Are you OK if we merge the PR for ESWIN EIC7700X SoC? I corrected the typos (also for 20 other files). Thanks :-)

[hartmannathan]

Sorry @hartmannathan: Are you OK if we merge the PR for ESWIN EIC7700X SoC? I corrected the typos (also for 20 other files). Thanks :-)

@lupyuen Yes! LGTM, thanks for your patience, I merged it just now :-)