WIP for VU13P MPP CM fw

[dacieri]

Hey @dacieri, I am trying to create a new project for the MPP prototype, but it fails with the following error:

ERROR: [DRC RTSTAT-2] Partially routed nets: 291 net(s) are partially routed. The problem bus(es) and/or net(s) are c2csslave_wrapper_1/c2cSlave_i/K_C2C_PHY/inst/c2cSlave_K_C2C_PHY_0_core_i/c2cSlave_K_C2C_PHY_0_wrapper_i/c2cSlave_K_C2C_PHY_0_multi_gt_i/c2cSlave_K_C2C_PHY_0_gt_i/inst/gen_gtwizard_gtye4_top.c2cSlave_K_C2C_PHY_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gte4_drp_arb_i/DADDR_O_reg[9]_0[9:0], c2csslave_wrapper_1/c2cSlave_i/K_C2C_PHY/inst/c2cSlave_K_C2C_PHY_0_core_i/c2cSlave_K_C2C_PHY_0_wrapper_i/c2cSlave_K_C2C_PHY_0_multi_gt_i/c2cSlave_K_C2C_PHY_0_gt_i/inst/gen_gtwizard_gtye4_top.c2cSlave_K_C2C_PHY_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gte4_drp_arb_i/DI_O_reg[15]_0[15:0], c2csslave_wrapper_1/c2cSlave_i/K_C2C_PHY/inst/c2cSlave_K_C2C_PHY_0_core_i/c2cSlave_K_C2C_PHY_0_wrapper_i/block_sync_sm_gtx0_i/D[0], c2csslave_wrapper_1/c2cSlave_i/K_C2C_PHY/inst/c2cSlave_K_C2C_PHY_0_core_i/c2cSlave_K_C2C_PHY_0_wrapper_i/c2cSlave_K_C2C_PHY_0_multi_gt_i/c2cSlave_K_C2C_PHY_0_gt_i/inst/gen_gtwizard_gtye4_top.c2cSlave_K_C2C_PHY_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/D[15:0], C2C_INTF_1/C2C_INTF_1/K_C2C_PHY_DEBUG_eyescanreset[0], C2C_INTF_1/C2C_INTF_1/K_C2C_PHY_DEBUG_eyescantrigger[0], C2C_INTF_1/C2C_INTF_1/K_C2C_PHY_DEBUG_rxbufreset[0], C2C_INTF_1/C2C_INTF_1/K_C2C_PHY_DEBUG_rxdfelpmreset[0], C2C_INTF_1/C2C_INTF_1/K_C2C_PHY_DEBUG_rxpcsreset[0], C2C_INTF_1/C2C_INTF_1/K_C2C_PHY_DEBUG_rxpmareset[0], C2C_INTF_1/GENERATE_LANE_LOOP[1].pacd_1/K_C2C_PHY_DEBUG_rxprbscntreset[0], C2C_INTF_1/C2C_INTF_1/K_C2C_PHY_DEBUG_txpcsreset[0], C2C_INTF_1/GENERATE_LANE_LOOP[1].pacd_2/K_C2C_PHY_DEBUG_txprbsforceerr[0], c2csslave_wrapper_1/c2cSlave_i/K_C2C_PHY/inst/c2cSlave_K_C2C_PHY_0_core_i/c2cSlave_K_C2C_PHY_0_wrapper_i/scrambler_64b66b_gtx0_i/SCRAMBLED_DATA_OUT_reg[63]_0[63:0], c2csslave_wrapper_1/c2cSlave_i/K_C2C_PHY/inst/c2cSlave_K_C2C_PHY_0_core_i/c2cSlave_K_C2C_PHY_0_wrapper_i/c2cSlave_K_C2C_PHY_0_multi_gt_i/c2cSlave_K_C2C_PHY_0_gt_i/inst/gen_gtwizard_gtye4_top.c2cSlave_K_C2C_PHY_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_pwrgood_delay_inst[0].delay_powergood_inst/TXRATE[0]... and (the first 15 of 65 listed). 

Any idea of what could be wrong?

[dgastler]

sigh... switch the order of the two C2C links

[dacieri]

sigh... switch the order of the two C2C links

so c2c <-> c2cb ? @dgastler