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| 1 | +extern crate alloc; |
| 2 | +use crate::vcpu::Aarch64VCpu; |
| 3 | +use aarch64_cpu::registers::{Readable, Writeable}; |
| 4 | +use aarch64_cpu::registers::{CNTFRQ_EL0, CNTPCT_EL0, CNTP_CTL_EL0, CNTP_TVAL_EL0}; |
| 5 | +use aarch64_sysreg::SystemRegType; |
| 6 | +use alloc::sync::Arc; |
| 7 | +use alloc::{vec, vec::Vec}; |
| 8 | +// pub use arm_gicv2::GicInterface; |
| 9 | +use axvcpu::AxVCpuHal; |
| 10 | +use axvcpu::{AxArchVCpu, AxVCpu}; |
| 11 | +use lazy_static::lazy_static; |
| 12 | +use spin::RwLock; |
| 13 | + |
| 14 | +type RegVcpu = Arc<AxVCpu<Aarch64VCpu>>; |
| 15 | + |
| 16 | +/// Struct representing an entry in the emulator register list. |
| 17 | +pub struct EmuRegEntry { |
| 18 | + /// The type of the emulator register. |
| 19 | + pub emu_type: EmuRegType, |
| 20 | + /// The address associated with the emulator register. |
| 21 | + pub addr: SystemRegType, |
| 22 | + /// The handler write function for the emulator register. |
| 23 | + pub handle_write: fn(SystemRegType, usize, u64, RegVcpu) -> bool, |
| 24 | + /// The handler read function for the emulator register. |
| 25 | + pub handle_read: fn(SystemRegType, usize, RegVcpu) -> bool, |
| 26 | +} |
| 27 | + |
| 28 | +/// Enumeration representing the type of emulator registers. |
| 29 | +pub enum EmuRegType { |
| 30 | + /// System register type for emulator registers. |
| 31 | + SysReg, |
| 32 | +} |
| 33 | + |
| 34 | +pub fn emu_register_add( |
| 35 | + addr: SystemRegType, |
| 36 | + handle_write: fn(SystemRegType, usize, u64, RegVcpu) -> bool, |
| 37 | + handle_read: fn(SystemRegType, usize, RegVcpu) -> bool, |
| 38 | +) { |
| 39 | + let mut emu_reg = EMU_REGISTERS.write(); |
| 40 | + for entry in emu_reg.iter() { |
| 41 | + if entry.addr == addr { |
| 42 | + error!("Register:{} already exists", addr); |
| 43 | + return; |
| 44 | + } |
| 45 | + } |
| 46 | + info!("Register:{} added", addr); |
| 47 | + emu_reg.push(EmuRegEntry { |
| 48 | + emu_type: EmuRegType::SysReg, |
| 49 | + addr, |
| 50 | + handle_write, |
| 51 | + handle_read, |
| 52 | + }); |
| 53 | +} |
| 54 | + |
| 55 | +pub fn emu_register_handle_write( |
| 56 | + addr: SystemRegType, |
| 57 | + reg: usize, |
| 58 | + value: u64, |
| 59 | + vcpu: RegVcpu, |
| 60 | +) -> bool { |
| 61 | + let emu_reg = EMU_REGISTERS.read(); |
| 62 | + for entry in emu_reg.iter() { |
| 63 | + if entry.addr == addr { |
| 64 | + return (entry.handle_write)(addr, reg, value, vcpu); |
| 65 | + } |
| 66 | + } |
| 67 | + panic!("Invalid emulated register write: addr={}", addr); |
| 68 | +} |
| 69 | + |
| 70 | +pub fn emu_register_handle_read(addr: SystemRegType, reg: usize, vcpu: RegVcpu) -> bool { |
| 71 | + let emu_reg = EMU_REGISTERS.read(); |
| 72 | + for entry in emu_reg.iter() { |
| 73 | + if entry.addr == addr { |
| 74 | + return (entry.handle_read)(addr, reg, vcpu); |
| 75 | + } |
| 76 | + } |
| 77 | + panic!("Invalid emulated register read: addr={}", addr); |
| 78 | +} |
| 79 | + |
| 80 | +fn handle_write(addr: SystemRegType, _reg: usize, value: u64, _vcpu: RegVcpu) -> bool { |
| 81 | + info!( |
| 82 | + "write to emulated register: addr: {}, value: {:x}", |
| 83 | + addr, value |
| 84 | + ); |
| 85 | + false |
| 86 | +} |
| 87 | +fn handle_read(addr: SystemRegType, _reg: usize, _vcpu: RegVcpu) -> bool { |
| 88 | + info!("read from emulated register: addr: {}", addr); |
| 89 | + false |
| 90 | +} |
| 91 | + |
| 92 | +lazy_static! { |
| 93 | + static ref EMU_REGISTERS: RwLock<Vec<EmuRegEntry>> = RwLock::new(vec![ |
| 94 | + EmuRegEntry { |
| 95 | + emu_type: EmuRegType::SysReg, |
| 96 | + addr: SystemRegType::CNTPCT_EL0, |
| 97 | + handle_write: handle_write, |
| 98 | + handle_read: |_addr, reg, vcpu| { |
| 99 | + // Get the current value of CNTPCT_EL0 |
| 100 | + // info!("Read CNTPCT_EL0"); |
| 101 | + (*vcpu).set_gpr(reg, CNTPCT_EL0.get() as usize); |
| 102 | + true |
| 103 | + }, |
| 104 | + }, |
| 105 | + EmuRegEntry { |
| 106 | + emu_type: EmuRegType::SysReg, |
| 107 | + addr: SystemRegType::CNTP_TVAL_EL0, |
| 108 | + handle_write: |_addr, _reg, value, _vcpu| { |
| 109 | + info!("Write CNTP_TVAL_EL0 0x{:x}",value); |
| 110 | + CNTP_TVAL_EL0.set(value); |
| 111 | + true |
| 112 | + }, |
| 113 | + handle_read: handle_read, |
| 114 | + }, |
| 115 | + EmuRegEntry { |
| 116 | + emu_type: EmuRegType::SysReg, |
| 117 | + addr: SystemRegType::CNTP_CTL_EL0, |
| 118 | + handle_write: |_addr, _reg, value, _vcpu| { |
| 119 | + // CNTP_CTL_EL0.set(value); |
| 120 | + // CNTP_TVAL_EL0.set(value); |
| 121 | + // axhal::irq::register_handler(30, || { |
| 122 | + // info!("Timer Interrupt"); |
| 123 | + // }); |
| 124 | + info!("Set Timer Interrupt: {}", value); |
| 125 | + axhal::arch::enable_irqs(); |
| 126 | + true |
| 127 | + }, |
| 128 | + handle_read: handle_read, |
| 129 | + }, |
| 130 | + EmuRegEntry { |
| 131 | + emu_type: EmuRegType::SysReg, |
| 132 | + addr: SystemRegType::CNTP_CVAL_EL0, |
| 133 | + handle_write: handle_write, |
| 134 | + handle_read: handle_read, |
| 135 | + }, |
| 136 | + ]); |
| 137 | +} |
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