feat: use RustSBI 0.4.0 proc macros to simplify VCpu SBI implementation

Cargo.toml

@@ -11,8 +11,9 @@ bit_field = "0.10"
 
 riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
 riscv-decode = { git = "https://github.com/KuangjuX/riscv-decode.git" }
-sbi-spec = { version = "0.0.6", features = ["legacy"] }
-sbi-rt = { version = "0.0.2", features = ["integer-impls", "legacy"] }
+rustsbi = { version = "0.4.0", features = ["forward"] }
+sbi-spec = { version = "0.0.7", features = ["legacy"] }
+sbi-rt = { version = "0.0.3", features = ["integer-impls", "legacy"] }
 tock-registers = "0.8.1"
 memoffset = { version = ">=0.6.5", features = ["unstable_const"] }
 

src/detect.rs

@@ -147,7 +147,7 @@ struct TrapFrame {
 // handle exceptions only rather than interrupts.
 #[naked]
 unsafe extern "C" fn on_detect_trap() -> ! {
-    asm!(
+    core::arch::naked_asm!(
         ".p2align 2",
         "addi   sp, sp, -8*21",
         "sd     ra, 0*8(sp)",
@@ -205,6 +205,5 @@ unsafe extern "C" fn on_detect_trap() -> ! {
         "addi   sp, sp, 8*21",
         "sret",
         rust_detect_trap = sym rust_detect_trap,
-        options(noreturn),
     )
 }

src/lib.rs

@@ -2,7 +2,6 @@
 #![feature(doc_cfg)]
 #![feature(naked_functions)]
 #![feature(riscv_ext_intrinsics)]
-#![feature(asm_const)]
 #![doc = include_str!("../README.md")]
 
 #[macro_use]
@@ -12,7 +11,6 @@ pub mod csrs;
 mod detect;
 mod percpu;
 mod regs;
-pub mod sbi;
 mod vcpu;
 
 pub use self::percpu::RISCVPerCpu;