fix: restore target specific dependencies

Author: AsakuraMizu

Cargo.lock

@@ -15,14 +15,21 @@ rust-version.workspace = true
 [features]
 arm-el2 = []
 
-all = []
+all = ["dep:aarch64-cpu", "dep:x86_64"]
 
 [dependencies]
 bitflags = "2.9"
 memory_addr.workspace = true
 
-[dev-dependencies]
+# Target-specific dependencies
+aarch64-cpu = { version = "10.0", optional = true }
+x86_64 = { version = "0.15", optional = true }
+
+[target.'cfg(target_arch = "aarch64")'.dependencies]
 aarch64-cpu = "10.0"
 
+[target.'cfg(target_arch = "x86_64")'.dependencies]
+x86_64 = "0.15"
+
 [package.metadata.docs.rs]
 all-features = true

page_table_entry/Cargo.toml

@@ -98,20 +98,17 @@ impl DescriptorAttr {
 impl MemAttr {
     /// The MAIR_ELx register should be set to this value to match the memory
     /// attributes in the descriptors.
-    ///
-    /// ```
-    /// # use aarch64_cpu::registers::MAIR_EL1;
-    /// # use page_table_entry::aarch64::MemAttr;
-    /// // Device-nGnRE memory
-    /// let attr0 = MAIR_EL1::Attr0_Device::nonGathering_nonReordering_EarlyWriteAck.value;
-    /// // Normal memory
-    /// let attr1 = MAIR_EL1::Attr1_Normal_Inner::WriteBack_NonTransient_ReadWriteAlloc.value
-    ///     | MAIR_EL1::Attr1_Normal_Outer::WriteBack_NonTransient_ReadWriteAlloc.value;
-    /// let attr2 = MAIR_EL1::Attr2_Normal_Inner::NonCacheable.value
-    ///     + MAIR_EL1::Attr2_Normal_Outer::NonCacheable.value;
-    /// assert_eq!(MemAttr::MAIR_VALUE, attr0 | attr1 | attr2);
-    /// ```
-    pub const MAIR_VALUE: u64 = 0x44_ff_04;
+    pub const MAIR_VALUE: u64 = {
+        use aarch64_cpu::registers::MAIR_EL1;
+        // Device-nGnRE memory
+        let attr0 = MAIR_EL1::Attr0_Device::nonGathering_nonReordering_EarlyWriteAck.value;
+        // Normal memory
+        let attr1 = MAIR_EL1::Attr1_Normal_Inner::WriteBack_NonTransient_ReadWriteAlloc.value
+            | MAIR_EL1::Attr1_Normal_Outer::WriteBack_NonTransient_ReadWriteAlloc.value;
+        let attr2 = MAIR_EL1::Attr2_Normal_Inner::NonCacheable.value
+            + MAIR_EL1::Attr2_Normal_Outer::NonCacheable.value;
+        attr0 | attr1 | attr2
+    };
 }
 
 impl From<DescriptorAttr> for MappingFlags {

page_table_entry/src/arch/aarch64.rs

@@ -2,76 +2,10 @@
 
 use core::fmt;
 use memory_addr::PhysAddr;
+use x86_64::structures::paging::page_table::PageTableFlags as PTF;
 
 use crate::{GenericPTE, MappingFlags};
 
-bitflags::bitflags! {
-    /// Possible flags for a page table entry.
-    ///
-    /// Reference: https://docs.rs/crate/x86_64/0.15.2/source/src/structures/paging/page_table.rs
-    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
-    pub struct PTF: u64 {
-        /// Specifies whether the mapped frame or page table is loaded in memory.
-        const PRESENT =         1;
-        /// Controls whether writes to the mapped frames are allowed.
-        ///
-        /// If this bit is unset in a level 1 page table entry, the mapped frame is read-only.
-        /// If this bit is unset in a higher level page table entry the complete range of mapped
-        /// pages is read-only.
-        const WRITABLE =        1 << 1;
-        /// Controls whether accesses from userspace (i.e. ring 3) are permitted.
-        const USER_ACCESSIBLE = 1 << 2;
-        /// If this bit is set, a “write-through” policy is used for the cache, else a “write-back”
-        /// policy is used.
-        const WRITE_THROUGH =   1 << 3;
-        /// Disables caching for the pointed entry is cacheable.
-        const NO_CACHE =        1 << 4;
-        /// Set by the CPU when the mapped frame or page table is accessed.
-        const ACCESSED =        1 << 5;
-        /// Set by the CPU on a write to the mapped frame.
-        const DIRTY =           1 << 6;
-        /// Specifies that the entry maps a huge frame instead of a page table. Only allowed in
-        /// P2 or P3 tables.
-        const HUGE_PAGE =       1 << 7;
-        /// Indicates that the mapping is present in all address spaces, so it isn't flushed from
-        /// the TLB on an address space switch.
-        const GLOBAL =          1 << 8;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_9 =           1 << 9;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_10 =          1 << 10;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_11 =          1 << 11;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_52 =          1 << 52;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_53 =          1 << 53;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_54 =          1 << 54;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_55 =          1 << 55;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_56 =          1 << 56;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_57 =          1 << 57;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_58 =          1 << 58;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_59 =          1 << 59;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_60 =          1 << 60;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_61 =          1 << 61;
-        /// Available to the OS, can be used to store additional data, e.g. custom flags.
-        const BIT_62 =          1 << 62;
-        /// Forbid code execution from the mapped frames.
-        ///
-        /// Can be only used when the no-execute page protection feature is enabled in the EFER
-        /// register.
-        const NO_EXECUTE =      1 << 63;
-    }
-}
-
 impl From<PTF> for MappingFlags {
     fn from(f: PTF) -> Self {
         if !f.contains(PTF::PRESENT) {

page_table_entry/src/arch/x86_64.rs

@@ -16,16 +16,20 @@ rust-version.workspace = true
 default = []
 copy-from = ["dep:bitmaps"]
 
-all = ["page_table_entry/all"]
+all = ["page_table_entry/all", "dep:riscv", "dep:x86_64"]
 
 [dependencies]
 log = "0.4"
 memory_addr.workspace = true
 page_table_entry.workspace = true
 bitmaps = { version = "3.2", default-features = false, optional = true }
 
+# Target-specific dependencies
+riscv = { version = "0.14", default-features = false, optional = true }
+x86_64 = { version = "0.15", optional = true }
+
 [target.'cfg(target_arch = "x86_64")'.dependencies]
-x86 = "0.52"
+x86_64 = "0.15"
 
 [target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
 riscv = { version = "0.14", default-features = false }

page_table_multiarch/Cargo.toml

@@ -12,14 +12,11 @@ pub trait SvVirtAddr: memory_addr::MemoryAddr + Send + Sync {
 impl SvVirtAddr for memory_addr::VirtAddr {
     #[inline]
     fn flush_tlb(vaddr: Option<Self>) {
-        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
         if let Some(vaddr) = vaddr {
             riscv::asm::sfence_vma(0, vaddr.as_usize())
         } else {
             riscv::asm::sfence_vma_all();
         }
-        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
-        let _ = vaddr;
     }
 }
 

page_table_multiarch/src/arch/riscv.rs

@@ -14,16 +14,11 @@ impl PagingMetaData for X64PagingMetaData {
 
     #[inline]
     fn flush_tlb(vaddr: Option<memory_addr::VirtAddr>) {
-        #[cfg(target_arch = "x86_64")]
-        unsafe {
-            if let Some(vaddr) = vaddr {
-                x86::tlb::flush(vaddr.into());
-            } else {
-                x86::tlb::flush_all();
-            }
+        if let Some(vaddr) = vaddr {
+            x86_64::instructions::tlb::flush(x86_64::VirtAddr::new(vaddr.as_usize() as u64));
+        } else {
+            x86_64::instructions::tlb::flush_all();
         }
-        #[cfg(not(target_arch = "x86_64"))]
-        let _ = vaddr;
     }
 }