arceos-org · AsakuraMizu · Nov 21, 2025 · Nov 21, 2025 · Nov 21, 2025 · Nov 21, 2025
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -27,9 +27,7 @@ jobs:
       run: cargo build --target ${{ matrix.targets }} --all-features
     - name: Unit test
       if: ${{ matrix.targets == 'x86_64-unknown-linux-gnu' }}
-      env:
-          RUSTFLAGS: --cfg doc
-      run: cargo test --target ${{ matrix.targets }} -- --nocapture
+      run: cargo test --target ${{ matrix.targets }} --all-features -- --nocapture
 
   doc:
     runs-on: ubuntu-latest
@@ -39,13 +37,11 @@ jobs:
       contents: write
     env:
       default-branch: ${{ format('refs/heads/{0}', github.event.repository.default_branch) }}
-      RUSTFLAGS: --cfg doc
       RUSTDOCFLAGS: -Zunstable-options --enable-index-page -D rustdoc::broken_intra_doc_links -D missing-docs
     steps:
     - uses: actions/checkout@v4
     - uses: dtolnay/rust-toolchain@nightly
     - name: Build docs
-      continue-on-error: ${{ github.ref != env.default-branch && github.event_name != 'pull_request' }}
       run: cargo doc --no-deps --all-features
     - name: Deploy to Github Pages
       if: ${{ github.ref == env.default-branch }}

diff --git a/Cargo.lock b/Cargo.lock
diff --git a/page_table_entry/Cargo.toml b/page_table_entry/Cargo.toml
@@ -15,15 +15,21 @@ rust-version.workspace = true
 [features]
 arm-el2 = []
 
+all = ["dep:aarch64-cpu", "dep:x86_64"]
+
 [dependencies]
 bitflags = "2.9"
 memory_addr.workspace = true
 
-[target.'cfg(any(target_arch = "aarch64", doc))'.dependencies]
+# Target-specific dependencies
+aarch64-cpu = { version = "10.0", optional = true }
+x86_64 = { version = "0.15", default-features = false, optional = true }
+
+[target.'cfg(target_arch = "aarch64")'.dependencies]
 aarch64-cpu = "10.0"
 
-[target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
-x86_64 = "0.15.2"
+[target.'cfg(target_arch = "x86_64")'.dependencies]
+x86_64 = { version = "0.15", default-features = false }
 
 [package.metadata.docs.rs]
-rustc-args = ["--cfg", "doc"]
+all-features = true
diff --git a/page_table_entry/README.md b/page_table_entry/README.md
@@ -27,7 +27,6 @@ methods for manipulating various page table entries.
 
 ```rust
 use memory_addr::PhysAddr;
-use x86_64::structures::paging::page_table::PageTableFlags;
 use page_table_entry::{GenericPTE, MappingFlags, x86_64::X64PTE};
 
 let paddr = PhysAddr::from(0x233000);

diff --git a/page_table_entry/src/arch/aarch64.rs b/page_table_entry/src/arch/aarch64.rs
@@ -1,6 +1,5 @@
 //! AArch64 VMSAv8-64 translation table format descriptors.
 
-use aarch64_cpu::registers::MAIR_EL1;
 use core::fmt;
 use memory_addr::PhysAddr;
 
@@ -100,6 +99,7 @@ impl MemAttr {
     /// The MAIR_ELx register should be set to this value to match the memory
     /// attributes in the descriptors.
     pub const MAIR_VALUE: u64 = {
+        use aarch64_cpu::registers::MAIR_EL1;
         // Device-nGnRE memory
         let attr0 = MAIR_EL1::Attr0_Device::nonGathering_nonReordering_EarlyWriteAck.value;
         // Normal memory

diff --git a/page_table_entry/src/arch/mod.rs b/page_table_entry/src/arch/mod.rs
@@ -1,11 +1,11 @@
-#[cfg(any(target_arch = "x86_64", doc))]
+#[cfg(any(target_arch = "x86_64", feature = "all"))]
 pub mod x86_64;
 
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", feature = "all"))]
 pub mod riscv;
 
-#[cfg(any(target_arch = "aarch64", doc))]
+#[cfg(any(target_arch = "aarch64", feature = "all"))]
 pub mod aarch64;
 
-#[cfg(any(target_arch = "loongarch64", doc))]
+#[cfg(any(target_arch = "loongarch64", feature = "all"))]
 pub mod loongarch64;
diff --git a/page_table_multiarch/Cargo.toml b/page_table_multiarch/Cargo.toml
@@ -16,20 +16,25 @@ rust-version.workspace = true
 default = []
 copy-from = ["dep:bitmaps"]
 
+all = ["page_table_entry/all"]
+
 [dependencies]
 log = "0.4"
 memory_addr.workspace = true
 page_table_entry.workspace = true
 bitmaps = { version = "3.2", default-features = false, optional = true }
 
-[target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
-x86 = "0.52"
+# Target-specific dependencies
+[target.'cfg(target_arch = "x86_64")'.dependencies]
+x86_64 = { version = "0.15", default-features = false, features = [
+    "instructions",
+] }
 
-[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))'.dependencies]
+[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
 riscv = { version = "0.14", default-features = false }
 
-[package.metadata.docs.rs]
-rustc-args = ["--cfg", "doc"]
-
 [dev-dependencies]
 rand = { version = "0.9.1", default-features = false, features = ["small_rng"] }
+
+[package.metadata.docs.rs]
+all-features = true
diff --git a/page_table_multiarch/src/arch/aarch64.rs b/page_table_multiarch/src/arch/aarch64.rs
@@ -1,6 +1,5 @@
 //! AArch64 specific page table structures.
 
-use core::arch::asm;
 use page_table_entry::aarch64::A64PTE;
 
 use crate::{PageTable64, PagingMetaData};
@@ -21,16 +20,22 @@ impl PagingMetaData for A64PagingMetaData {
 
     #[inline]
     fn flush_tlb(vaddr: Option<memory_addr::VirtAddr>) {
+        #[cfg(target_arch = "aarch64")]
         unsafe {
             if let Some(vaddr) = vaddr {
                 // TLB Invalidate by VA, All ASID, EL1, Inner Shareable
                 const VA_MASK: usize = (1 << 44) - 1; // VA[55:12] => bits[43:0]
-                asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) ((vaddr.as_usize() >> 12) & VA_MASK))
+                core::arch::asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) ((vaddr.as_usize() >> 12) & VA_MASK))
             } else {
                 // TLB Invalidate by VMID, All at stage 1, EL1
-                asm!("tlbi vmalle1; dsb sy; isb")
+                core::arch::asm!("tlbi vmalle1; dsb sy; isb")
             }
         }
+        #[cfg(not(target_arch = "aarch64"))]
+        {
+            let _ = vaddr;
+            unimplemented!()
+        }
     }
 }
 

diff --git a/page_table_multiarch/src/arch/loongarch64.rs b/page_table_multiarch/src/arch/loongarch64.rs
@@ -1,7 +1,6 @@
 //! LoongArch64 specific page table structures.
 
 use crate::{PageTable64, PagingMetaData};
-use core::arch::asm;
 use page_table_entry::loongarch64::LA64PTE;
 
 /// Metadata of LoongArch64 page tables.
@@ -48,6 +47,7 @@ impl PagingMetaData for LA64MetaData {
 
     #[inline]
     fn flush_tlb(vaddr: Option<memory_addr::VirtAddr>) {
+        #[cfg(target_arch = "loongarch64")]
         unsafe {
             if let Some(vaddr) = vaddr {
                 // <https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_dbar>
@@ -66,12 +66,17 @@ impl PagingMetaData for LA64MetaData {
                 //
                 // When the operation indicated by op does not require an ASID, the
                 // general register rj should be set to r0.
-                asm!("dbar 0; invtlb 0x05, $r0, {reg}", reg = in(reg) vaddr.as_usize());
+                core::arch::asm!("dbar 0; invtlb 0x05, $r0, {reg}", reg = in(reg) vaddr.as_usize());
             } else {
                 // op 0x0: Clear all page table entries
-                asm!("dbar 0; invtlb 0x00, $r0, $r0");
+                core::arch::asm!("dbar 0; invtlb 0x00, $r0, $r0");
             }
         }
+        #[cfg(not(target_arch = "loongarch64"))]
+        {
+            let _ = vaddr;
+            unimplemented!()
+        }
     }
 }
 

diff --git a/page_table_multiarch/src/arch/mod.rs b/page_table_multiarch/src/arch/mod.rs
@@ -1,11 +1,11 @@
-#[cfg(any(target_arch = "x86_64", doc))]
+#[cfg(any(target_arch = "x86_64", feature = "all"))]
 pub mod x86_64;
 
-#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", feature = "all"))]
 pub mod riscv;
 
-#[cfg(any(target_arch = "aarch64", doc))]
+#[cfg(any(target_arch = "aarch64", feature = "all"))]
 pub mod aarch64;
 
-#[cfg(any(target_arch = "loongarch64", doc))]
+#[cfg(any(target_arch = "loongarch64", feature = "all"))]
 pub mod loongarch64;
diff --git a/page_table_multiarch/src/arch/riscv.rs b/page_table_multiarch/src/arch/riscv.rs
@@ -3,15 +3,6 @@
 use crate::{PageTable64, PagingMetaData};
 use page_table_entry::riscv::Rv64PTE;
 
-#[inline]
-fn riscv_flush_tlb(vaddr: Option<memory_addr::VirtAddr>) {
-    if let Some(vaddr) = vaddr {
-        riscv::asm::sfence_vma(0, vaddr.as_usize())
-    } else {
-        riscv::asm::sfence_vma_all();
-    }
-}
-
 /// A virtual address that can be used in RISC-V Sv39 and Sv48 page tables.
 pub trait SvVirtAddr: memory_addr::MemoryAddr + Send + Sync {
     /// Flush the TLB.
@@ -21,7 +12,17 @@ pub trait SvVirtAddr: memory_addr::MemoryAddr + Send + Sync {
 impl SvVirtAddr for memory_addr::VirtAddr {
     #[inline]
     fn flush_tlb(vaddr: Option<Self>) {
-        riscv_flush_tlb(vaddr.map(|vaddr| vaddr.into()))
+        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        if let Some(vaddr) = vaddr {
+            riscv::asm::sfence_vma(0, vaddr.as_usize())
+        } else {
+            riscv::asm::sfence_vma_all();
+        }
+        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
+        {
+            let _ = vaddr;
+            unimplemented!()
+        }
     }
 }
 

diff --git a/page_table_multiarch/src/arch/x86_64.rs b/page_table_multiarch/src/arch/x86_64.rs
@@ -14,12 +14,16 @@ impl PagingMetaData for X64PagingMetaData {
 
     #[inline]
     fn flush_tlb(vaddr: Option<memory_addr::VirtAddr>) {
-        unsafe {
-            if let Some(vaddr) = vaddr {
-                x86::tlb::flush(vaddr.into());
-            } else {
-                x86::tlb::flush_all();
-            }
+        #[cfg(target_arch = "x86_64")]
+        if let Some(vaddr) = vaddr {
+            x86_64::instructions::tlb::flush(x86_64::VirtAddr::new(vaddr.as_usize() as u64));
+        } else {
+            x86_64::instructions::tlb::flush_all();
+        }
+        #[cfg(not(target_arch = "x86_64"))]
+        {
+            let _ = vaddr;
+            unimplemented!()
         }
     }
 }

diff --git a/page_table_multiarch/tests/alloc_tests.rs b/page_table_multiarch/tests/alloc_tests.rs
@@ -91,6 +91,7 @@ fn run_test_for<M: PagingMetaData<VirtAddr = VirtAddr>, PTE: GenericPTE>() -> Pa
 }
 
 #[test]
+#[cfg(any(target_arch = "x86_64", feature = "all"))]
 fn test_dealloc_x86() -> PagingResult<()> {
     run_test_for::<
         page_table_multiarch::x86_64::X64PagingMetaData,
@@ -100,6 +101,7 @@ fn test_dealloc_x86() -> PagingResult<()> {
 }
 
 #[test]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", feature = "all"))]
 fn test_dealloc_riscv() -> PagingResult<()> {
     run_test_for::<
         page_table_multiarch::riscv::Sv39MetaData<VirtAddr>,
@@ -113,6 +115,7 @@ fn test_dealloc_riscv() -> PagingResult<()> {
 }
 
 #[test]
+#[cfg(any(target_arch = "aarch64", feature = "all"))]
 fn test_dealloc_aarch64() -> PagingResult<()> {
     run_test_for::<
         page_table_multiarch::aarch64::A64PagingMetaData,
@@ -122,6 +125,7 @@ fn test_dealloc_aarch64() -> PagingResult<()> {
 }
 
 #[test]
+#[cfg(any(target_arch = "loongarch64", feature = "all"))]
 fn test_dealloc_loongarch64() -> PagingResult<()> {
     run_test_for::<
         page_table_multiarch::loongarch64::LA64MetaData,