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hathachhathach
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able to response with good crc
1 parent b893f1d commit 9b7dee5

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9 files changed

+253
-71
lines changed

9 files changed

+253
-71
lines changed

‎examples/typec/power_delivery/src/main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ int main(void)
5454
board_init();
5555
board_led_write(true);
5656

57-
tuc_init(0, TYPEC_PORT_SNK);
57+
tuc_init(0, TUSB_TYPEC_PORT_SNK);
5858

5959
uint32_t start_ms = 0;
6060
bool led_state = false;

‎src/common/tusb_mcu.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,12 +197,17 @@
197197
#define TUP_DCD_ENDPOINT_MAX 9
198198

199199
#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
200+
// Device controller
200201
#define TUP_USBIP_FSDEV
201202
#define TUP_USBIP_FSDEV_STM32
203+
204+
// TypeC controller
202205
#define TUP_USBIP_TYPEC_STM32
203206

204207
#define TUP_DCD_ENDPOINT_MAX 8
205208

209+
#define TUP_TYPEC_RHPORTS_NUM 1
210+
206211
#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
207212
#define TUP_USBIP_FSDEV
208213
#define TUP_USBIP_FSDEV_STM32

‎src/common/tusb_types.h

Lines changed: 61 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -504,75 +504,85 @@ TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
504504
//--------------------------------------------------------------------+
505505

506506
typedef enum {
507-
TYPEC_PORT_SRC,
508-
TYPEC_PORT_SNK,
509-
TYPEC_PORT_DRP
510-
} typec_port_type_t;
507+
TUSB_TYPEC_PORT_SRC,
508+
TUSB_TYPEC_PORT_SNK,
509+
TUSB_TYPEC_PORT_DRP
510+
} tusb_typec_port_type_t;
511511

512512
typedef enum {
513-
TYPEC_MSG_CTRL_RESERVED = 0, // 0b00000: 0
514-
TYPEC_MSG_CTRL_GOOD_CRC, // 0b00001: 1
515-
TYPEC_MSG_CTRL_GO_TO_MIN, // 0b00010: 2
516-
TYPEC_MSG_CTRL_ACCEPT, // 0b00011: 3
517-
TYPEC_MSG_CTRL_REJECT, // 0b00100: 4
518-
TYPEC_MSG_CTRL_PING, // 0b00101: 5
519-
TYPEC_MSG_CTRL_PS_RDY, // 0b00110: 6
520-
TYPEC_MSG_CTRL_GET_SOURCE_CAP, // 0b00111: 7
521-
TYPEC_MSG_CTRL_GET_SINK_CAP, // 0b01000: 8
522-
TYPEC_MSG_CTRL_DR_SWAP, // 0b01001: 9
523-
TYPEC_MSG_CTRL_PR_SWAP, // 0b01010: 10
524-
TYPEC_MSG_CTRL_VCONN_SWAP, // 0b01011: 11
525-
TYPEC_MSG_CTRL_WAIT, // 0b01100: 12
526-
TYPEC_MSG_CTRL_SOFT_RESET, // 0b01101: 13
527-
TYPEC_MSG_CTRL_DATA_RESET, // 0b01110: 14
528-
TYPEC_MSG_CTRL_DATA_RESET_COMPLETE, // 0b01111: 15
529-
TYPEC_MSG_CTRL_NOT_SUPPORTED, // 0b10000: 16
530-
TYPEC_MSG_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
531-
TYPEC_MSG_CTRL_GET_STATUS, // 0b10010: 18
532-
TYPEC_MSG_CTRL_FR_SWAP, // 0b10011: 19
533-
TYPEC_MSG_CTRL_GET_PPS_STATUS, // 0b10100: 20
534-
TYPEC_MSG_CTRL_GET_COUNTRY_CODES, // 0b10101: 21
535-
TYPEC_MSG_CTRL_GET_SINK_CAP_EXTENDED, // 0b10110: 22
536-
TYPEC_MSG_CTRL_GET_SOURCE_INFO, // 0b10111: 23
537-
TYPEC_MSG_CTRL_REVISION, // 0b11000: 24
538-
} typec_msg_ctrl_type_t;
513+
TUSB_PD_CTRL_RESERVED = 0, // 0b00000: 0
514+
TUSB_PD_CTRL_GOOD_CRC, // 0b00001: 1
515+
TUSB_PD_CTRL_GO_TO_MIN, // 0b00010: 2
516+
TUSB_PD_CTRL_ACCEPT, // 0b00011: 3
517+
TUSB_PD_CTRL_REJECT, // 0b00100: 4
518+
TUSB_PD_CTRL_PING, // 0b00101: 5
519+
TUSB_PD_CTRL_PS_RDY, // 0b00110: 6
520+
TUSB_PD_CTRL_GET_SOURCE_CAP, // 0b00111: 7
521+
TUSB_PD_CTRL_GET_SINK_CAP, // 0b01000: 8
522+
TUSB_PD_CTRL_DR_SWAP, // 0b01001: 9
523+
TUSB_PD_CTRL_PR_SWAP, // 0b01010: 10
524+
TUSB_PD_CTRL_VCONN_SWAP, // 0b01011: 11
525+
TUSB_PD_CTRL_WAIT, // 0b01100: 12
526+
TUSB_PD_CTRL_SOFT_RESET, // 0b01101: 13
527+
TUSB_PD_CTRL_DATA_RESET, // 0b01110: 14
528+
TUSB_PD_CTRL_DATA_RESET_COMPLETE, // 0b01111: 15
529+
TUSB_PD_CTRL_NOT_SUPPORTED, // 0b10000: 16
530+
TUSB_PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
531+
TUSB_PD_CTRL_GET_STATUS, // 0b10010: 18
532+
TUSB_PD_CTRL_FR_SWAP, // 0b10011: 19
533+
TUSB_PD_CTRL_GET_PPS_STATUS, // 0b10100: 20
534+
TUSB_PD_CTRL_GET_COUNTRY_CODES, // 0b10101: 21
535+
TUSB_PD_CTRL_GET_SINK_CAP_EXTENDED, // 0b10110: 22
536+
TUSB_PD_CTRL_GET_SOURCE_INFO, // 0b10111: 23
537+
TUSB_PD_CTRL_REVISION, // 0b11000: 24
538+
} tusb_pd_ctrl_type_t;
539539

540540
typedef enum {
541-
TYPEC_MSG_DATA_RESERVED = 0, // 0b00000: 0
542-
TYPEC_MSG_DATA_SOURCE_CAP, // 0b00001: 1
543-
TYPEC_MSG_DATA_REQUEST, // 0b00010: 2
544-
TYPEC_MSG_DATA_BIST, // 0b00011: 3
545-
TYPEC_MSG_DATA_SINK_CAP, // 0b00100: 4
546-
TYPEC_MSG_DATA_BATTERY_STATUS, // 0b00101: 5
547-
TYPEC_MSG_DATA_ALERT, // 0b00110: 6
548-
TYPEC_MSG_DATA_GET_COUNTRY_INFO, // 0b00111: 7
549-
TYPEC_MSG_DATA_ENTER_USB, // 0b01000: 8
550-
TYPEC_MSG_DATA_EPR_REQUEST, // 0b01001: 9
551-
TYPEC_MSG_DATA_EPR_MODE, // 0b01010: 10
552-
TYPEC_MSG_DATA_SRC_INFO, // 0b01011: 11
553-
TYPEC_MSG_DATA_REVISION, // 0b01100: 12
554-
TYPEC_MSG_DATA_RESERVED_13, // 0b01101: 13
555-
TYPEC_MSG_DATA_RESERVED_14, // 0b01110: 14
556-
TYPEC_MSG_DATA_VENDOR_DEFINED, // 0b01111: 15
557-
} typec_msg_data_type_t;
541+
TUSB_PD_DATA_RESERVED = 0, // 0b00000: 0
542+
TUSB_PD_DATA_SOURCE_CAP, // 0b00001: 1
543+
TUSB_PD_DATA_REQUEST, // 0b00010: 2
544+
TUSB_PD_DATA_BIST, // 0b00011: 3
545+
TUSB_PD_DATA_SINK_CAP, // 0b00100: 4
546+
TUSB_PD_DATA_BATTERY_STATUS, // 0b00101: 5
547+
TUSB_PD_DATA_ALERT, // 0b00110: 6
548+
TUSB_PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7
549+
TUSB_PD_DATA_ENTER_USB, // 0b01000: 8
550+
TUSB_PD_DATA_EPR_REQUEST, // 0b01001: 9
551+
TUSB_PD_DATA_EPR_MODE, // 0b01010: 10
552+
TUSB_PD_DATA_SRC_INFO, // 0b01011: 11
553+
TUSB_PD_DATA_REVISION, // 0b01100: 12
554+
TUSB_PD_DATA_RESERVED_13, // 0b01101: 13
555+
TUSB_PD_DATA_RESERVED_14, // 0b01110: 14
556+
TUSB_PD_DATA_VENDOR_DEFINED, // 0b01111: 15
557+
} tusb_pd_data_type_t;
558+
559+
enum {
560+
TUSB_PD_REV10 = 0x0,
561+
TUSB_PD_REV20 = 0x1,
562+
TUSB_PD_REV30 = 0x2,
563+
};
558564

559565
typedef struct TU_ATTR_PACKED {
560566
uint16_t msg_type : 5; // [0:4]
561-
uint16_t data_role : 1; // [5] SOP only
567+
uint16_t data_role : 1; // [5] SOP only: 0 UFP, 1 DFP
562568
uint16_t specs_rev : 2; // [6:7]
563-
uint16_t power_role : 1; // [8] SOP only
569+
uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source
564570
uint16_t msg_id : 3; // [9:11]
565571
uint16_t n_data_obj : 3; // [12:14]
566572
uint16_t extended : 1; // [15]
567-
} tusb_typec_message_header_t;
573+
} tusb_pd_header_t;
574+
575+
TU_VERIFY_STATIC( sizeof(tusb_pd_header_t) == 2, "size is not correct");
568576

569577
typedef struct TU_ATTR_PACKED {
570578
uint16_t data_size : 9; // [0:8]
571579
uint16_t reserved : 1; // [9]
572580
uint16_t request_chunk : 1; // [10]
573581
uint16_t chunk_number : 4; // [11:14]
574582
uint16_t chunked : 1; // [15]
575-
} tusb_typec_message_header_extended_t;
583+
} tusb_pd_header_extended_t;
584+
585+
TU_VERIFY_STATIC( sizeof(tusb_pd_header_extended_t) == 2, "size is not correct");
576586

577587

578588
TU_ATTR_PACKED_END // End of all packed definitions

‎src/device/usbd.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,9 +252,19 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
252252
drvid -= _app_driver_count;
253253
}
254254

255+
// when there is no built-in drivers BUILTIN_DRIVER_COUNT = 0 will cause -Wtype-limits warning
256+
#ifdef __GNUC__
257+
#pragma GCC diagnostic push
258+
#pragma GCC diagnostic ignored "-Wtype-limits"
259+
#endif
260+
255261
// Built-in drivers
256262
if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid];
257263

264+
#ifdef __GNUC__
265+
#pragma GCC diagnostic pop
266+
#endif
267+
258268
return NULL;
259269
}
260270

‎src/host/usbh.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -724,7 +724,7 @@ uint8_t* usbh_get_enum_buf(void)
724724

725725
void usbh_int_set(bool enabled)
726726
{
727-
// TODO all host controller if multiple is used
727+
// TODO all host controller if multiple are used since they shared the same event queue
728728
if (enabled)
729729
{
730730
hcd_int_enable(_usbh_controller);

‎src/portable/st/typec/typec_stm32.c

Lines changed: 91 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -29,20 +29,43 @@
2929

3030
#include "common/tusb_common.h"
3131

32-
#include "stm32g4xx.h"
32+
#if CFG_TUSB_MCU == OPT_MCU_STM32G4
33+
#include "stm32g4xx.h"
34+
#else
35+
#error "Unsupported STM32 family"
36+
#endif
3337

3438
//--------------------------------------------------------------------+
3539
//
3640
//--------------------------------------------------------------------+
37-
uint8_t pd_rx_buf[262];
38-
uint32_t pd_rx_count = 0;
39-
uint8_t pd_rx_order_set;
41+
42+
#define PHY_SYNC1 0x18u
43+
#define PHY_SYNC2 0x11u
44+
#define PHY_SYNC3 0x06u
45+
#define PHY_RST1 0x07u
46+
#define PHY_RST2 0x19u
47+
#define PHY_EOP 0x0Du
48+
49+
#define PHY_ORDERED_SET_SOP (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC2<<15u)) // SOP Ordered set coding
50+
#define PHY_ORDERED_SET_SOP_P (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC3<<15u)) // SOP' Ordered set coding
51+
#define PHY_ORDERED_SET_SOP_PP (PHY_SYNC1 | (PHY_SYNC3<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC3<<15u)) // SOP'' Ordered set coding
52+
#define PHY_ORDERED_SET_HARD_RESET (PHY_RST1 | (PHY_RST1<<5u) | (PHY_RST1<<10u) | (PHY_RST2<<15u )) // Hard Reset Ordered set coding
53+
#define PHY_ORDERED_SET_CABLE_RESET (PHY_RST1 | (PHY_SYNC1<<5u) | (PHY_RST1<<10u) | (PHY_SYNC3<<15u)) // Cable Reset Ordered set coding
54+
#define PHY_ORDERED_SET_SOP_P_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u) | (PHY_RST2<<10u) | (PHY_SYNC3<<15u)) // SOP' Debug Ordered set coding
55+
#define PHY_ORDERED_SET_SOP_PP_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC2<<15u)) // SOP'' Debug Ordered set coding
56+
57+
58+
static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4);
59+
static uint32_t rx_count = 0;
60+
61+
static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
62+
static uint32_t tx_count;
4063

4164
//--------------------------------------------------------------------+
4265
//
4366
//--------------------------------------------------------------------+
4467

45-
bool tcd_init(uint8_t rhport, typec_port_type_t port_type) {
68+
bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
4669
(void) rhport;
4770

4871
// Initialization phase: CFG1
@@ -52,7 +75,7 @@ bool tcd_init(uint8_t rhport, typec_port_type_t port_type) {
5275
UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
5376

5477
// General programming sequence (with UCPD configured then enabled)
55-
if (port_type == TYPEC_PORT_SNK) {
78+
if (port_type == TUSB_TYPEC_PORT_SNK) {
5679
// Enable both CC Phy
5780
UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
5881

@@ -83,6 +106,19 @@ void tcd_int_disable(uint8_t rhport) {
83106
NVIC_DisableIRQ(UCPD1_IRQn);
84107
}
85108

109+
bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
110+
(void) rhport;
111+
112+
return true;
113+
}
114+
115+
bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) {
116+
(void) rhport;
117+
(void) buffer;
118+
(void) total_bytes;
119+
return false;
120+
}
121+
86122
void tcd_int_handler(uint8_t rhport) {
87123
(void) rhport;
88124

@@ -116,7 +152,7 @@ void tcd_int_handler(uint8_t rhport) {
116152

117153
if (cr & UCPD_CR_PHYRXEN) {
118154
// Enable Interrupt
119-
UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
155+
UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
120156
UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
121157
UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
122158
}
@@ -128,13 +164,13 @@ void tcd_int_handler(uint8_t rhport) {
128164
UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
129165
}
130166

131-
//------------- Receive -------------//
167+
//------------- RX -------------//
132168
if (sr & UCPD_SR_RXORDDET) {
133169
// SOP: Start of Packet.
134-
pd_rx_order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
170+
// UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
135171

136172
// reset count when received SOP
137-
pd_rx_count = 0;
173+
rx_count = 0;
138174

139175
// ack
140176
UCPD1->ICR = UCPD_ICR_RXORDDETCF;
@@ -143,17 +179,38 @@ void tcd_int_handler(uint8_t rhport) {
143179
if (sr & UCPD_SR_RXNE) {
144180
// TODO DMA later
145181
do {
146-
pd_rx_buf[pd_rx_count++] = UCPD1->RXDR;
182+
rx_buf[rx_count++] = UCPD1->RXDR;
147183
} while (UCPD1->SR & UCPD_SR_RXNE);
184+
185+
// no ack needed
148186
}
149187

188+
// End of message
150189
if (sr & UCPD_SR_RXMSGEND) {
151-
// End of message
152190

153191
// Skip if CRC failed
154192
if (!(sr & UCPD_SR_RXERR)) {
155193
uint32_t payload_size = UCPD1->RX_PAYSZ;
156-
TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count);
194+
// TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count);
195+
196+
tusb_pd_header_t const* rx_header = (tusb_pd_header_t const*) rx_buf;
197+
(*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) {
198+
.msg_type = TUSB_PD_CTRL_GOOD_CRC,
199+
.data_role = 0, // UFP
200+
.specs_rev = TUSB_PD_REV30,
201+
.power_role = 0, // Sink
202+
.msg_id = rx_header->msg_id,
203+
.n_data_obj = 0,
204+
.extended = 0
205+
};
206+
tx_count = 0;
207+
208+
// response with good crc
209+
UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
210+
UCPD1->TX_PAYSZ = 2;
211+
UCPD1->CR |= UCPD_CR_TXSEND; // will trigger TXIS interrupt
212+
213+
// notify stack after good crc ?
157214
}
158215

159216
// ack
@@ -162,11 +219,31 @@ void tcd_int_handler(uint8_t rhport) {
162219

163220
if (sr & UCPD_SR_RXOVR) {
164221
TU_LOG1("RXOVR\n");
165-
TU_LOG1_HEX(pd_rx_count);
222+
TU_LOG1_HEX(rx_count);
166223
// ack
167224
UCPD1->ICR = UCPD_ICR_RXOVRCF;
168225
}
169226

227+
//------------- TX -------------//
228+
if (sr & UCPD_SR_TXIS) {
229+
// TU_LOG1("TXIS\n");
230+
231+
// TODO DMA later
232+
do {
233+
UCPD1->TXDR = tx_buf[tx_count++];
234+
} while (UCPD1->SR & UCPD_SR_TXIS);
235+
236+
// no ack needed
237+
}
238+
239+
if (sr & UCPD_SR_TXMSGSENT) {
240+
// all byte sent
241+
TU_LOG1("TXMSGSENT\n");
242+
243+
// ack
244+
UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
245+
}
246+
170247
// if (sr & UCPD_SR_RXNE) {
171248
// uint8_t data = UCPD1->RXDR;
172249
// pd_rx_buf[pd_rx_count++] = data;

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