This repository provides a port of FreeRTOS for the Renesas R9A02G021 RISC-V Processor. It implements a simple demo derived from the FreeRTOS "blinky" demo applications.
- Full FreeRTOS port
- Minimal boot code
- Own BSP (no dependencies for Renesas BSP)
- Support for both vectored and trap interrupt handling
- Support for UART trace
- Support for assert
- Support for exceptions
- Support for HW based stack limit check
FBF-R9A02G021 board
- Clone this repository recursively (to include the submodules):
$ git clone --recurse-submodules https://github.com/akimari-
Install Renesas RISC-V toolchain:
https://llvm-gcc-renesas.com/riscv/riscv-download-toolchains/
-
Compile blinker application:
$ make- Compiled blinker.elf is on build/ directory
The clock is configured to 32MHz.
The FreeRTOS parts are configured:
FreeRTOSConfig.h(customize according to your needs)
UART trace port is UART0. This is /dev/tty on Linux dev env.