My experience in mixed-signal IC modeling and verification has given me a deep understanding of hardware and a broad perspective that spans both design and validation. Building on this foundation, I am currently focusing on the field of SoC verification using SystemVerilog and UVM.
Languages & HDLs: Verilog, SystemVerilog, C, Python
EDA Tools & Simulators: Virtuoso, Xcelium, VCS, HSPICE, Spectre, FineSim, XMODEL
Verification Methodologies: UVM (Universal Verification Methodology)
Operating Systems: Linux, WSL (Windows Subsystem for Linux)
UCIe: Behavioral modeling for system-level simulation
TX Driver: Modeling and verification for custom SoC implementation
CDR: Modeling and verification for functional correctness
ADC/DAC: Modeling and verification of mixed-signal behavior
UART: Synthesizable RTL design and verification
