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Fix pcie sata link training rkvendor 6.1 for rock-5-itx #8471

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Fix pcie sata link training rkvendor 6.1 for rock-5-itx #8471

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@prahal prahal commented Aug 8, 2025 •
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Description

Disable common refclk for the pcie phy on rock-5-itx.
On Radxa rock-5-itx the SATA endpoint was unstable. Most of the time, the drives attached to it were not detected.

Jira reference number AR-2561 (though this fix is only applied for the vendor kernel on rock-5-itx)

Mind it could be, this PR should go to https://github.com/armbian/linux-rockchip.

How Has This Been Tested?

Booted ten times in a row. Usually three times was enough to get no drives detected.

  • lsblk -f
  • smartcl -a /dev/sda
    both on 6.1.115-vendor-rk35xx

Checklist:

Please delete options that are not relevant.

  • My code follows the style guidelines of this project
  • I have performed a self-review of my own code
  • I have commented my code, particularly in hard-to-understand areas
  • My changes generate no new warnings

prahal added 2 commits August 8, 2025 03:45
@prahal
UPSTREAM: Add support for rockchip,rx-common-refclk-mode
0a4152e 
>From the RK3588 Technical Reference Manual, Part1,
section 6.19 PCIe3PHY_GRF Register Description:
"rxX_cmn_refclk_mode"
RX common reference clock mode for lane X. This mode should be enabled
only when the far-end and near-end devices are running with a common
reference clock.

The hardware reset value for this field is 0x1 (enabled).
Note that this register field is only available on RK3588, not on RK3568.

The link training either fails or is highly unstable (link state will jump
continuously between L0 and recovery) when this mode is enabled while
using an endpoint running in Separate Reference Clock with No SSC (SRNS)
mode or Separate Reference Clock with SSC (SRIS) mode.
(Which is usually the case when using a real SoC as endpoint, e.g. the
RK3588 PCIe controller can run in both Root Complex and Endpoint mode.)

Add support for the device tree property rockchip,rx-common-refclk-mode,
such that the PCIe PHY can be used in configurations where the Root
Complex and Endpoint are not using a common reference clock.

Signed-off-by: Niklas Cassel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Signed-off-by: Alban Browaeys <[email protected]>
(cherry picked from commit a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66)
@prahal
rock-5-itx: Fix PCI SATA link training instability
781ebcd 
Signed-off-by: Alban Browaeys <[email protected]>
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coderabbitai bot commented Aug 8, 2025

Important

Review skipped

Review was skipped due to path filters

⛔ Files ignored due to path filters (2)
  • patch/kernel/rk35xx-vendor-6.1/0001-phy-rockchip-snps-pcie3-add-support-for-rockchip-rx-.patch is excluded by !patch/**
  • patch/kernel/rk35xx-vendor-6.1/board-rock-5-itx-dts-fix-sata-pcie.patch is excluded by !patch/**

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@github-actions github-actions bot added size/medium PR with more then 50 and less then 250 lines 08 Milestone: Third quarter release Needs review Seeking for review Hardware Hardware related like kernel, U-Boot, ... Patches Patches related to kernel, U-Boot, ... labels Aug 8, 2025
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Mind it could be, this PR should go to https://github.com/armbian/linux-rockchip.

Yes, please sumbit there.

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prahal commented Aug 10, 2025

Closing, replaced by armbian linux-rockchip PR armbian/linux-rockchip#382

@prahal prahal closed this Aug 10, 2025
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