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sm8550-6.18: Fix TF card IO performance regression #9546
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Merged
igorpecovnik
merged 1 commit into
armbian:main
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kasimling:odin2_fix_sdcard_io_perf_2
Mar 23, 2026
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−8
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32 changes: 32 additions & 0 deletions
32
patch/kernel/archive/sm8550-6.18/0215-drivers-mmc-Added-qcom-downstream-sdhci-driver.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,32 @@ | ||
| From 8ed623bd2f04dc319da87d2ed5bed24cff30818d Mon Sep 17 00:00:00 2001 | ||
| From: Alex Ling <ling_kasim@hotmail.com> | ||
| Date: Fri, 23 Jan 2026 09:29:36 +0800 | ||
| Subject: [PATCH 1/3] drivers: mmc: Added qcom downstream sdhci driver | ||
|
|
||
| --- | ||
| drivers/mmc/host/sdhci-msm-downstream.c | 2 -- | ||
| 1 file changed, 2 deletions(-) | ||
|
|
||
| diff --git a/drivers/mmc/host/sdhci-msm-downstream.c b/drivers/mmc/host/sdhci-msm-downstream.c | ||
| index 41fd45fbe100..4cc1b2fde376 100644 | ||
| --- a/drivers/mmc/host/sdhci-msm-downstream.c | ||
| +++ b/drivers/mmc/host/sdhci-msm-downstream.c | ||
| @@ -5633,7 +5633,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) | ||
| if (!IS_ERR(msm_host->bus_clk)) | ||
| clk_disable_unprepare(msm_host->bus_clk); | ||
| pltfm_free: | ||
| - sdhci_pltfm_free(pdev); | ||
| return ret; | ||
| } | ||
|
|
||
| @@ -5696,7 +5695,6 @@ static void sdhci_msm_remove(struct platform_device *pdev) | ||
| sdhci_msm_bus_get_and_set_vote(host, 0); | ||
| sdhci_msm_bus_unregister(&pdev->dev, msm_host); | ||
| } | ||
| - sdhci_pltfm_free(pdev); | ||
| } | ||
|
|
||
| static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev) | ||
| -- | ||
| 2.43.0 | ||
|
|
36 changes: 36 additions & 0 deletions
36
...ernel/archive/sm8550-6.18/0216-Revert-clk-qcom-gcc-sm8550-Use-floor-ops-for-SDCC-RC.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,36 @@ | ||
| From 8f40d4ac02f20b672ec66a5f1bbcddd913749a29 Mon Sep 17 00:00:00 2001 | ||
| From: Alex Ling <ling_kasim@hotmail.com> | ||
| Date: Wed, 4 Mar 2026 22:48:48 +0800 | ||
| Subject: [PATCH 2/3] Revert "clk: qcom: gcc-sm8550: Use floor ops for SDCC | ||
| RCGs" | ||
|
|
||
| This reverts commit b714c1d0bb437e46b1bb82fea5d0a138bbfe6f98. | ||
| --- | ||
| drivers/clk/qcom/gcc-sm8550.c | 4 ++-- | ||
| 1 file changed, 2 insertions(+), 2 deletions(-) | ||
|
|
||
| diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c | ||
| index 36a5b7de5b55..862a9bf73bcb 100644 | ||
| --- a/drivers/clk/qcom/gcc-sm8550.c | ||
| +++ b/drivers/clk/qcom/gcc-sm8550.c | ||
| @@ -1025,7 +1025,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { | ||
| .parent_data = gcc_parent_data_9, | ||
| .num_parents = ARRAY_SIZE(gcc_parent_data_9), | ||
| .flags = CLK_SET_RATE_PARENT, | ||
| - .ops = &clk_rcg2_shared_floor_ops, | ||
| + .ops = &clk_rcg2_shared_ops, | ||
| }, | ||
| }; | ||
|
|
||
| @@ -1048,7 +1048,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { | ||
| .parent_data = gcc_parent_data_0, | ||
| .num_parents = ARRAY_SIZE(gcc_parent_data_0), | ||
| .flags = CLK_SET_RATE_PARENT, | ||
| - .ops = &clk_rcg2_shared_floor_ops, | ||
| + .ops = &clk_rcg2_shared_ops, | ||
| }, | ||
| }; | ||
|
|
||
| -- | ||
| 2.43.0 | ||
|
|
211 changes: 211 additions & 0 deletions
211
...ernel/archive/sm8550-6.18/0217-arm64-dts-Switch-to-downstream-sdhc-driver-for-Odin2.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,211 @@ | ||
| From ccfc44521cb9133569b1ace1c51efb80a4aaf925 Mon Sep 17 00:00:00 2001 | ||
| From: Alex Ling <ling_kasim@hotmail.com> | ||
| Date: Mon, 16 Mar 2026 16:02:50 +0800 | ||
| Subject: [PATCH 3/3] arm64: dts: Switch to downstream sdhc driver for Odin2 | ||
|
|
||
| Signed-off-by: Alex Ling <ling_kasim@hotmail.com> | ||
| --- | ||
| .../arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 86 +++++++++++++++++ | ||
| .../boot/dts/qcom/qcs8550-ayn-odin2portal.dts | 95 +++++++++++++++++++ | ||
| 2 files changed, 181 insertions(+) | ||
|
|
||
| diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | ||
| index 98cf638b24f4..08fbffc250b3 100644 | ||
| --- a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | ||
| +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | ||
| @@ -321,3 +321,89 @@ &spk_amp_r { | ||
| firmware-name = "qcom/sm8550/ayn/odin2/aw883xx_acf.bin"; | ||
| }; | ||
|
|
||
| +/delete-node/ &sdhc_2; | ||
| + | ||
| +&soc { | ||
| + sdhc_2: sdhci@8804000 { | ||
| + compatible = "qcom,sdhci-msm-v5-downstream"; | ||
| + reg = <0 0x08804000 0 0x1000>; | ||
| + reg-names = "hc_mem"; | ||
| + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, | ||
| + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| + interrupt-names = "hc_irq", "pwr_irq"; | ||
| + bus-width = <4>; | ||
| + no-sdio; | ||
| + no-mmc; | ||
| + qcom,restore-after-cx-collapse; | ||
| + qcom,uses_level_shifter; | ||
| + qcom,dll_lock_bist_fail_wa; | ||
| + clocks = <&gcc GCC_SDCC2_AHB_CLK>, | ||
| + <&gcc GCC_SDCC2_APPS_CLK>; | ||
| + clock-names = "iface", "core"; | ||
| + | ||
| + /* | ||
| + * DLL HSR settings. Refer go/hsr - <Target> DLL settings. | ||
| + * Note that the DLL_CONFIG_2 value is not passed from the | ||
| + * device tree, 0 but it is calculated in the driver. | ||
| + */ | ||
| + qcom,dll-hsr-list = <0x0007442C 0x0 0x10 | ||
| + 0x090106C0 0x80040868>; | ||
| + | ||
| + iommus = <&apps_smmu 0x540 0x0>; | ||
| + dma-coherent; | ||
| + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, | ||
| + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; | ||
| + interconnect-names = "sdhc-ddr", "cpu-sdhc"; | ||
| + | ||
| + qcom,msm-bus,name = "sdhc2"; | ||
| + qcom,msm-bus,num-cases = <0x07>; | ||
| + qcom,msm-bus,num-paths = <0x02>; | ||
| + qcom,msm-bus,vectors-KBps = <0x00 0x00 0x00 0x00 0x416 0xc80 0x640 0x640 0xff50 0x3d090 0x186a0 0x208c8 0x1fe9e 0x3d090 0x208c8 0x208c8 0x3fd3e 0x3d090 0x249f0 0x208c8 0x3fd3e 0xc3500 0x493e0 0x493e0 0x146cc2 0x3e8000 0x146cc2 0x3e8000>; | ||
| + qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | ||
| + | ||
| + operating-points-v2 = <&sdhc2_opp_table>; | ||
| + | ||
| + vdd-supply = <&vreg_l9b_2p9>; | ||
| + qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>; | ||
| + qcom,vdd-current-level = <0x00 0xc3500>; | ||
| + | ||
| + vdd-io-supply = <&vreg_l8b_1p8>; | ||
| + qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; | ||
| + qcom,vdd-io-current-level = <0x00 0x15e0>; | ||
| + | ||
| + pinctrl-names = "default", "sleep"; | ||
| + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; | ||
| + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; | ||
| + | ||
| + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; | ||
| + resets = <&gcc GCC_SDCC2_BCR>; | ||
| + reset-names = "core_reset"; | ||
| + | ||
| + qos0 { | ||
| + mask = <0xf0>; | ||
| + vote = <0x2c>; | ||
| + }; | ||
| + | ||
| + qos1 { | ||
| + mask = <0x0f>; | ||
| + vote = <0x2c>; | ||
| + }; | ||
| + | ||
| + sdhc2_opp_table: opp-table { | ||
| + compatible = "operating-points-v2"; | ||
| + | ||
| + opp-100000000 { | ||
| + opp-hz = <0x00 0x5f5e100>; | ||
| + opp-peak-kBps = <0x27100 0x186a0>; | ||
| + opp-avg-kBps = <0xc350 0x00>; | ||
| + }; | ||
| + | ||
| + opp-202000000 { | ||
| + opp-hz = <0x00 0xc0a4680>; | ||
| + opp-peak-kBps = <0x30d40 0x1d4c0>; | ||
| + opp-avg-kBps = <0x19640 0x00>; | ||
| + }; | ||
| + }; | ||
| + }; | ||
| +}; | ||
| + | ||
| diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts | ||
| index 70e7e64dc879..c0daa80caa31 100644 | ||
| --- a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts | ||
| +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts | ||
| @@ -292,3 +292,98 @@ &spk_amp_r { | ||
| firmware-name = "qcom/sm8550/ayn/odin2portal/aw883xx_acf.bin"; | ||
| }; | ||
|
|
||
| +/delete-node/ &sdhc2_opp_table; | ||
| +/delete-node/ &sdhc_2; | ||
| + | ||
| +&soc { | ||
| + qcom_tzlog: qcom_tzlog { | ||
| + status = "disabled"; | ||
| + }; | ||
| + | ||
| + arch_timer: arch_timer { | ||
| + status = "disabled"; | ||
| + }; | ||
| + | ||
| + sdhc_2: sdhci@8804000 { | ||
| + compatible = "qcom,sdhci-msm-v5-downstream"; | ||
| + reg = <0 0x08804000 0 0x1000>; | ||
| + reg-names = "hc_mem"; | ||
| + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, | ||
| + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| + interrupt-names = "hc_irq", "pwr_irq"; | ||
| + bus-width = <4>; | ||
| + no-sdio; | ||
| + no-mmc; | ||
| + qcom,restore-after-cx-collapse; | ||
| + qcom,uses_level_shifter; | ||
| + qcom,dll_lock_bist_fail_wa; | ||
| + clocks = <&gcc GCC_SDCC2_AHB_CLK>, | ||
| + <&gcc GCC_SDCC2_APPS_CLK>; | ||
| + clock-names = "iface", "core"; | ||
| + | ||
| + /* | ||
| + * DLL HSR settings. Refer go/hsr - <Target> DLL settings. | ||
| + * Note that the DLL_CONFIG_2 value is not passed from the | ||
| + * device tree, but it is calculated in the driver. | ||
| + */ | ||
| + qcom,dll-hsr-list = <0x0007442C 0x0 0x10 | ||
| + 0x090106C0 0x80040868>; | ||
| + | ||
| + iommus = <&apps_smmu 0x540 0x0>; | ||
| + dma-coherent; | ||
| + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, | ||
| + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; | ||
| + interconnect-names = "sdhc-ddr", "cpu-sdhc"; | ||
| + | ||
| + qcom,msm-bus,name = "sdhc2"; | ||
| + qcom,msm-bus,num-cases = <0x07>; | ||
| + qcom,msm-bus,num-paths = <0x02>; | ||
| + qcom,msm-bus,vectors-KBps = <0x00 0x00 0x00 0x00 0x416 0xc80 0x640 0x640 0xff50 0x3d090 0x186a0 0x208c8 0x1fe9e 0x3d090 0x208c8 0x208c8 0x3fd3e 0x3d090 0x249f0 0x208c8 0x3fd3e 0xc3500 0x493e0 0x493e0 0x146cc2 0x3e8000 0x146cc2 0x3e8000>; | ||
| + qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | ||
| + | ||
| + operating-points-v2 = <&sdhc2_opp_table>; | ||
| + | ||
| + vdd-supply = <&vreg_l9b_2p9>; | ||
| + qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>; | ||
| + qcom,vdd-current-level = <0x00 0xc3500>; | ||
| + | ||
| + vdd-io-supply = <&vreg_l8b_1p8>; | ||
| + qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; | ||
| + qcom,vdd-io-current-level = <0x00 0x15e0>; | ||
| + | ||
| + pinctrl-names = "default", "sleep"; | ||
| + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; | ||
| + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; | ||
| + | ||
| + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; | ||
| + resets = <&gcc GCC_SDCC2_BCR>; | ||
| + reset-names = "core_reset"; | ||
| + | ||
| + qos0 { | ||
| + mask = <0xf0>; | ||
| + vote = <0x2c>; | ||
| + }; | ||
| + | ||
| + qos1 { | ||
| + mask = <0x0f>; | ||
| + vote = <0x2c>; | ||
| + }; | ||
| + | ||
| + sdhc2_opp_table: opp-table { | ||
| + compatible = "operating-points-v2"; | ||
| + | ||
| + opp-100000000 { | ||
| + opp-hz = <0x00 0x5f5e100>; | ||
| + opp-peak-kBps = <0x27100 0x186a0>; | ||
| + opp-avg-kBps = <0xc350 0x00>; | ||
| + }; | ||
| + | ||
| + opp-202000000 { | ||
| + opp-hz = <0x00 0xc0a4680>; | ||
| + opp-peak-kBps = <0x30d40 0x1d4c0>; | ||
| + opp-avg-kBps = <0x19640 0x00>; | ||
| + }; | ||
| + }; | ||
| + }; | ||
| +}; | ||
| + | ||
| -- | ||
| 2.43.0 | ||
|
|
||
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