Added fix for issue riscv-software-src#164 (riscv-software-src#166)

james-ball-qualcomm · ayosher · commit 6d244d943f04 · 2024-11-20T19:23:36.000+02:00
Signed-off-by: Albert Yosher &lt;ayosher@qti.qualcomm.com&gt;
diff --git a/arch/crd/MC-1.yaml b/arch/crd/MC-1.yaml
@@ -63,6 +63,12 @@ MC-1:
         MTVAL_WIDTH: {} # Unconstrained
         MTVEC_MODES: {} # Unconstrained
         PHYS_ADDR_WIDTH: {} # Unconstrained
+        MISALIGNED_LDST: {} # Unconstrained
+        MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained
+        MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained
+        MISALIGNED_SPLIT_STRATEGY:
+          schema:
+            const: by_byte
         PRECISE_SYNCHRONOUS_EXCEPTIONS:
           schema:
             const: true
