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beckusbeckus
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Cleanup of timer code
Fix compile errors due to changes in core QEMU. Timer code still needs to be tested but the rest of the STM32 code passes unit tests...
1 parent 6d9adee commit caf90a6

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4 files changed

+38
-28
lines changed

4 files changed

+38
-28
lines changed

‎hw/arm/stm32.c

Lines changed: 17 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -144,8 +144,9 @@ static void stm32_create_timer_dev(
144144
DeviceState *afio_dev,
145145
hwaddr addr,
146146
qemu_irq *irq,
147-
int num_irqs)
147+
int num_irqs)
148148
{
149+
int i;
149150
char child_name[9];
150151
DeviceState *timer_dev = qdev_create(NULL, "stm32-timer");
151152
QDEV_PROP_SET_PERIPH_T(timer_dev, "periph", periph);
@@ -154,7 +155,12 @@ static void stm32_create_timer_dev(
154155
qdev_prop_set_ptr(timer_dev, "stm32_afio", afio_dev);
155156
snprintf(child_name, sizeof(child_name), "timer[%i]", timer_num);
156157
object_property_add_child(stm32_container, child_name, OBJECT(timer_dev), NULL);
157-
stm32_init_periph(timer_dev, periph, addr, irq, num_irqs);
158+
stm32_init_periph(timer_dev, periph, addr, NULL);
159+
for (i = 0; i < num_irqs; i++) {
160+
if (irq[i]) {
161+
sysbus_connect_irq(SYS_BUS_DEVICE(timer_dev), 0, irq[i]);
162+
}
163+
}
158164
}
159165

160166

@@ -203,7 +209,7 @@ void stm32_init(
203209
qdev_prop_set_uint32(rcc_dev, "osc_freq", osc_freq);
204210
qdev_prop_set_uint32(rcc_dev, "osc32_freq", osc32_freq);
205211
object_property_add_child(stm32_container, "rcc", OBJECT(rcc_dev), NULL);
206-
stm32_init_periph(rcc_dev, STM32_RCC, 0x40021000, pic[STM32_RCC_IRQ]);
212+
stm32_init_periph(rcc_dev, STM32_RCC_PERIPH, 0x40021000, pic[STM32_RCC_IRQ]);
207213

208214
DeviceState **gpio_dev = (DeviceState **)g_malloc0(sizeof(DeviceState *) * STM32_GPIO_COUNT);
209215
for(i = 0; i < STM32_GPIO_COUNT; i++) {
@@ -219,7 +225,7 @@ void stm32_init(
219225

220226
DeviceState *exti_dev = qdev_create(NULL, TYPE_STM32_EXTI);
221227
object_property_add_child(stm32_container, "exti", OBJECT(exti_dev), NULL);
222-
stm32_init_periph(exti_dev, STM32_EXTI, 0x40010400, NULL);
228+
stm32_init_periph(exti_dev, STM32_EXTI_PERIPH, 0x40010400, NULL);
223229
SysBusDevice *exti_busdev = SYS_BUS_DEVICE(exti_dev);
224230
sysbus_connect_irq(exti_busdev, 0, pic[STM32_EXTI0_IRQ]);
225231
sysbus_connect_irq(exti_busdev, 1, pic[STM32_EXTI1_IRQ]);
@@ -250,15 +256,13 @@ void stm32_init(
250256
stm32_create_uart_dev(stm32_container, STM32_UART3, 3, rcc_dev, gpio_dev, afio_dev, 0x40004800, pic[STM32_UART3_IRQ]);
251257
stm32_create_uart_dev(stm32_container, STM32_UART4, 4, rcc_dev, gpio_dev, afio_dev, 0x40004c00, pic[STM32_UART4_IRQ]);
252258
stm32_create_uart_dev(stm32_container, STM32_UART5, 5, rcc_dev, gpio_dev, afio_dev, 0x40005000, pic[STM32_UART5_IRQ]);
253-
254-
qemu_irq tim1_irqs[] = { pic[TIM1_BRK_IRQn], pic[TIM1_UP_IRQn], pic[TIM1_TRG_COM_IRQn],
255-
pic[TIM1_CC_IRQn]};
256-
stm32_create_timer_dev(stm32_container, STM32_TIM1, 1, rcc_dev, gpio_dev, afio_dev, 0x40012C00, tim1_irqs, 5);
257-
258-
stm32_create_timer_dev(stm32_container, STM32_TIM2, 1, rcc_dev, gpio_dev, afio_dev, 0x40000000, pic[TIM2_IRQn], 1);
259-
stm32_create_timer_dev(stm32_container, STM32_TIM3, 1, rcc_dev, gpio_dev, afio_dev, 0x40000400, pic[TIM3_IRQn], 1);
260-
stm32_create_timer_dev(stm32_container, STM32_TIM4, 1, rcc_dev, gpio_dev, afio_dev, 0x40000800, pic[TIM4_IRQn], 1);
261-
stm32_create_timer_dev(stm32_container, STM32_TIM5, 1, rcc_dev, gpio_dev, afio_dev, 0x40000C00, pic[TIM5_IRQn], 1);
262259

260+
qemu_irq tim1_irqs[] = { pic[TIM1_BRK_IRQn], pic[TIM1_UP_IRQn], pic[TIM1_TRG_COM_IRQn],
261+
pic[TIM1_CC_IRQn]};
262+
stm32_create_timer_dev(stm32_container, STM32_TIM1, 1, rcc_dev, gpio_dev, afio_dev, 0x40012C00, tim1_irqs, 5);
263263

264+
stm32_create_timer_dev(stm32_container, STM32_TIM2, 1, rcc_dev, gpio_dev, afio_dev, 0x40000000, &pic[TIM2_IRQn], 1);
265+
stm32_create_timer_dev(stm32_container, STM32_TIM3, 1, rcc_dev, gpio_dev, afio_dev, 0x40000400, &pic[TIM3_IRQn], 1);
266+
stm32_create_timer_dev(stm32_container, STM32_TIM4, 1, rcc_dev, gpio_dev, afio_dev, 0x40000800, &pic[TIM4_IRQn], 1);
267+
stm32_create_timer_dev(stm32_container, STM32_TIM5, 1, rcc_dev, gpio_dev, afio_dev, 0x40000C00, &pic[TIM5_IRQn], 1);
264268
}

‎hw/arm/stm32_rcc.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -881,14 +881,14 @@ static void stm32_rcc_init_clk(Stm32Rcc *s)
881881
s->PERIPHCLK[STM32_UART4] = clktree_create_clk("UART4", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
882882
s->PERIPHCLK[STM32_UART5] = clktree_create_clk("UART5", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
883883

884-
s->PERIPHCLK[STM32_TIM1] = stm32_clktree_create_clk("TIM1", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
885-
s->PERIPHCLK[STM32_TIM2] = stm32_clktree_create_clk("TIM2", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
886-
s->PERIPHCLK[STM32_TIM3] = stm32_clktree_create_clk("TIM3", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
887-
s->PERIPHCLK[STM32_TIM4] = stm32_clktree_create_clk("TIM4", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
888-
s->PERIPHCLK[STM32_TIM5] = stm32_clktree_create_clk("TIM5", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
889-
s->PERIPHCLK[STM32_TIM6] = stm32_clktree_create_clk("TIM6", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
890-
s->PERIPHCLK[STM32_TIM7] = stm32_clktree_create_clk("TIM7", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
891-
s->PERIPHCLK[STM32_TIM8] = stm32_clktree_create_clk("TIM8", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
884+
s->PERIPHCLK[STM32_TIM1] = clktree_create_clk("TIM1", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
885+
s->PERIPHCLK[STM32_TIM2] = clktree_create_clk("TIM2", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
886+
s->PERIPHCLK[STM32_TIM3] = clktree_create_clk("TIM3", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
887+
s->PERIPHCLK[STM32_TIM4] = clktree_create_clk("TIM4", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
888+
s->PERIPHCLK[STM32_TIM5] = clktree_create_clk("TIM5", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
889+
s->PERIPHCLK[STM32_TIM6] = clktree_create_clk("TIM6", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
890+
s->PERIPHCLK[STM32_TIM7] = clktree_create_clk("TIM7", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
891+
s->PERIPHCLK[STM32_TIM8] = clktree_create_clk("TIM8", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
892892
}
893893

894894

‎hw/timer/stm32_timer.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ enum
7272
TIMER_DOWN_COUNT = 1
7373
};
7474

75-
typedef struct {
75+
struct Stm32Timer {
7676

7777
/* Inherited */
7878
SysBusDevice busdev;
@@ -116,7 +116,7 @@ typedef struct {
116116
/* uint32_t dcr; DMA mode not supported */
117117
/* uint32_t dmar; DMA mode not supported */
118118

119-
} Stm32Timer;
119+
};
120120

121121
static void stm32_timer_freq(Stm32Timer *s)
122122
{
@@ -419,13 +419,13 @@ static int stm32_timer_init(SysBusDevice *dev)
419419
{
420420
QEMUBH *bh;
421421
qemu_irq *clk_irq;
422-
Stm32Timer *s = FROM_SYSBUS(Stm32Timer, dev);
422+
Stm32Timer *s = STM32_TIMER(dev);
423423

424424
s->stm32_rcc = (Stm32Rcc *)s->stm32_rcc_prop;
425425
s->stm32_gpio = (Stm32Gpio **)s->stm32_gpio_prop;
426426
s->stm32_afio = (Stm32Afio *)s->stm32_afio_prop;
427427

428-
memory_region_init_io(&s->iomem, &stm32_timer_ops, s, "stm32-timer", 0x1000);
428+
memory_region_init_io(&s->iomem, OBJECT(s), &stm32_timer_ops, s, "stm32-timer", 0x1000);
429429
sysbus_init_mmio(dev, &s->iomem);
430430

431431
sysbus_init_irq(dev, &s->irq);
@@ -456,7 +456,7 @@ static int stm32_timer_init(SysBusDevice *dev)
456456

457457
static void stm32_timer_pre_save(void *opaque)
458458
{
459-
Stm32Timer *s = opaque;
459+
//Stm32Timer *s = opaque;
460460

461461
/* tick_offset is base_time - rtc_clock base time. Instead, we want to
462462
* store the base time relative to the vm_clock for backwards-compatibility. */
@@ -466,7 +466,7 @@ static void stm32_timer_pre_save(void *opaque)
466466

467467
static int stm32_timer_post_load(void *opaque, int version_id)
468468
{
469-
Stm32Timer *s = opaque;
469+
//Stm32Timer *s = opaque;
470470

471471
//int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
472472
//s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
@@ -505,7 +505,7 @@ static void stm32_timer_class_init(ObjectClass *klass, void *data)
505505
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
506506

507507
k->init = stm32_timer_init;
508-
dc->no_user = 1;
508+
//dc->no_user = 1;
509509
dc->vmsd = &vmstate_stm32;
510510
dc->props = stm32_timer_properties;
511511
}

‎include/hw/arm/stm32.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -283,6 +283,12 @@ void stm32_uart_connect(Stm32Uart *s, CharDriverState *chr,
283283
uint32_t afio_board_map);
284284

285285

286+
/* Timer */
287+
typedef struct Stm32Timer Stm32Timer;
288+
289+
#define TYPE_STM32_TIMER "stm32-timer"
290+
#define STM32_TIMER(obj) OBJECT_CHECK(Stm32Timer, (obj), TYPE_STM32_TIMER)
291+
286292

287293

288294
/* STM32 MICROCONTROLLER - GENERAL */

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