Support primitive gates with names in Verilog netlist

[tklam]

Hi, I have modified the Verilog parser to allow reading primitive gates with names. The following Verilog code could not be parsed because the gates have names:

module top (a, b, c);
input a;
input b;
output c;

wire n1;

xor t1(n1, a, b);
or t2 (c, a, b, n1);
endmodule

This pull request allows it to be parsed successfully.