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Merged
alanminko merged 1 commit into from
Aug 29, 2025
Merged

rewire support timing-constraint #438

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22 changes: 11 additions & 11 deletions abclib.dsp
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39 changes: 22 additions & 17 deletions src/aig/gia/giaStoch.c
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Expand Up @@ -649,16 +649,31 @@ Gia_Man_t * Gia_ManDupFromArrays( Gia_Man_t * p, Vec_Int_t * vCis, Vec_Int_t * v
pObj->Value = Gia_ManAppendAnd( pNew, Gia_ObjFanin0Copy(pObj), Gia_ObjFanin1Copy(pObj) );
Gia_ManForEachObjVec( vCos, p, pObj, i )
pObj->Value = Gia_ManAppendCo( pNew, pObj->Value );
if ( vLevels[0] ) {
if ( vLevels[0] && vLevels[1] ) {
pNew->vCiArrs = Vec_IntAlloc( Gia_ManCiNum(pNew) );
Gia_ManForEachObjVec( vCis, p, pObj, i )
Vec_IntPush( pNew->vCiArrs, Gia_ObjLevel(p, pObj) );
Gia_ManForEachObjVec( vCis, p, pObj, i ) {
// Vec_IntPush( pNew->vCiArrs, Gia_ObjLevel(p, pObj) );
Vec_IntPush( pNew->vCiArrs, Vec_IntEntry(vLevels[0], Gia_ObjId(p, pObj)) );
}
pNew->vCoReqs = Vec_IntAlloc( Gia_ManCoNum(pNew) );
Gia_ManForEachObjVec( vCos, p, pObj, i )
Vec_IntPush( pNew->vCoReqs, nLevels - Gia_ObjLevel(p, pObj) );
Gia_ManForEachObjVec( vCos, p, pObj, i ) {
// Vec_IntPush( pNew->vCoReqs, nLevels - Gia_ObjLevel(p, pObj) );
Vec_IntPush( pNew->vCoReqs, nLevels + 1 - Vec_IntEntry(vLevels[1], Gia_ObjId(p, pObj)) );
assert( Gia_ObjIsAnd(pObj) );
}
}
return pNew;
}
int Gia_ManLevelR( Gia_Man_t * pMan )
{
int i, LevelMax = Gia_ManLevelRNum( pMan );
Gia_Obj_t * pNode;
Gia_ManForEachObj( pMan, pNode, i )
Gia_ObjSetLevel( pMan, pNode, (int)(LevelMax - Gia_ObjLevel(pMan, pNode) + 1) );
Gia_ManForEachCi( pMan, pNode, i )
Gia_ObjSetLevel( pMan, pNode, 0 );
return LevelMax;
}
Vec_Ptr_t * Gia_ManDupWindows( Gia_Man_t * pMan, Vec_Ptr_t * vvIns, Vec_Ptr_t * vvNodes, Vec_Ptr_t * vvOuts, int fDelayOpt )
{
// compute direct and reverse level
Expand All @@ -669,7 +684,7 @@ Vec_Ptr_t * Gia_ManDupWindows( Gia_Man_t * pMan, Vec_Ptr_t * vvIns, Vec_Ptr_t *
ABC_SWAP( Vec_Int_t *, vLevels[0], pMan->vLevels );
Levels[1] = Gia_ManLevelRNum( pMan );
ABC_SWAP( Vec_Int_t *, vLevels[1], pMan->vLevels );
assert( Levels[0] == Levels[1] );
assert( (Levels[0] + 1) == Levels[1] );
}
Vec_Int_t * vNodes; int i;
Vec_Ptr_t * vWins = Vec_PtrAlloc( Vec_PtrSize(vvIns) );
Expand All @@ -687,16 +702,6 @@ Vec_Ptr_t * Gia_ManDupWindows( Gia_Man_t * pMan, Vec_Ptr_t * vvIns, Vec_Ptr_t *
Vec_IntFreeP( &vLevels[1] );
return vWins;
}
int Gia_ManLevelR( Gia_Man_t * pMan )
{
int i, LevelMax = Gia_ManLevelRNum( pMan );
Gia_Obj_t * pNode;
Gia_ManForEachObj( pMan, pNode, i )
Gia_ObjSetLevel( pMan, pNode, (int)(LevelMax - Gia_ObjLevel(pMan, pNode) + 1) );
Gia_ManForEachCi( pMan, pNode, i )
Gia_ObjSetLevel( pMan, pNode, 0 );
return LevelMax;
}
Vec_Ptr_t * Gia_ManExtractPartitions( Gia_Man_t * pMan, int Iter, int nSuppMax, Vec_Ptr_t ** pvIns, Vec_Ptr_t ** pvOuts, Vec_Ptr_t ** pvNodes, int fOverlap, int fDelayOpt )
{
// if ( Gia_ManCiNum(pMan) <= nSuppMax ) {
Expand Down Expand Up @@ -816,7 +821,7 @@ Vec_Ptr_t * Gia_ManDupDivide( Gia_Man_t * p, Vec_Wec_t * vCis, Vec_Wec_t * vAnds
ABC_SWAP( Vec_Int_t *, vLevels[0], p->vLevels );
Levels[1] = Gia_ManLevelRNum( p );
ABC_SWAP( Vec_Int_t *, vLevels[1], p->vLevels );
assert( Levels[0] == Levels[1] );
// assert( Levels[0] == Levels[1] );
}
Vec_Ptr_t * vAigs = Vec_PtrAlloc( Vec_WecSize(vCis) ); int i;
for ( i = 0; i < Vec_WecSize(vCis); i++ )
Expand Down
48 changes: 32 additions & 16 deletions src/base/abci/abc.c
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Expand Up @@ -20987,17 +20987,17 @@ int Abc_CommandTimeScale( Abc_Frame_t * pAbc, int argc, char ** argv )
***********************************************************************/
int Abc_CommandRewire( Abc_Frame_t * pAbc, int argc, char ** argv )
{
extern Abc_Ntk_t *Abc_ManRewire(Abc_Ntk_t *pNtk, Gia_Man_t *pExc, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fCheck, int fVerbose);
extern Abc_Ntk_t *Abc_ManRewire(Abc_Ntk_t *pNtk, Gia_Man_t *pExc, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int fDch, int fTiming, int nSeed, int fCheck, int fVerbose);
Abc_Ntk_t *pNtk, *pTemp;
Gia_Man_t *pExc = NULL;
FILE *pFile = NULL;
int c, nIters = 100000, nExpands = 128, nGrowth = 4, nDivs = -1, nFaninMax = 8, nSeed = 1, nTimeOut = 0, nVerbose = 1, nMode = 0, nMappedMode = 0, nDist = 0, fCheck = 0;
int c, nIters = 100000, nExpands = 128, nGrowth = 4, nDivs = -1, nFaninMax = 8, nSeed = 1, nTimeOut = 0, nVerbose = 1, nMode = 0, nMappedMode = 0, nDist = 0, fCheck = 0, fDch = 1, fTiming = 0;
float nLevelGrowRatio = 0;
Extra_UtilGetoptReset();

pNtk = Abc_FrameReadNtk(pAbc);

while ( ( c = Extra_UtilGetopt( argc, argv, "IEGDFSTMALRCVch" ) ) != EOF ) {
while ( ( c = Extra_UtilGetopt( argc, argv, "IEGDFSTMALRCVdtch" ) ) != EOF ) {
switch ( c ) {
case 'I':
if ( globalUtilOptind >= argc )
Expand Down Expand Up @@ -21126,6 +21126,12 @@ int Abc_CommandRewire( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'c':
fCheck ^= 1;
break;
case 'd':
fDch ^= 1;
break;
case 't':
fTiming ^= 1;
break;
case 'h':
default:
goto usage;
Expand All @@ -21143,16 +21149,16 @@ int Abc_CommandRewire( Abc_Frame_t * pAbc, int argc, char ** argv )
}
if ( nMode == 0 && !Abc_NtkIsStrash(pNtk) )
{
Abc_Print( -1, "Rewiring works only for the AIG representation (run \"strash\").\n" );
Abc_Print( -1, "Rewiring operates only on specific network representations. Use \"strash\" to apply it to an AIG, or add the \"-M 1\" flag to enable it for a mapped network.\n" );
return 1;
}
if ( nMode >= 1 && Abc_FrameReadLibGen2() == NULL )
if ( nMode == 1 && Abc_FrameReadLibGen2() == NULL )
{
Abc_Print( -1, "Library is not available.\n" );
return 1;
}

pTemp = Abc_ManRewire( pNtk, pExc, nIters, nLevelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, nSeed, fCheck, nVerbose );
pTemp = Abc_ManRewire( pNtk, pExc, nIters, nLevelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, fDch, fTiming, nSeed, fCheck, nVerbose );
if ( pExc )
Gia_ManStop( pExc );
Abc_FrameReplaceCurrentNetwork( pAbc, pTemp );
Expand All @@ -21167,13 +21173,15 @@ int Abc_CommandRewire( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Print( -2, "\t-F <num> : the limit on the fanin count at a node [default = %d]\n", nFaninMax);
Abc_Print( -2, "\t-L <num> : localization distances (0: unlimited) [default = %d]\n", nDist);
Abc_Print( -2, "\t-R <num> : level constraint (0: unlimited, 1: preserve level) [default = %g]\n", nLevelGrowRatio);
Abc_Print( -2, "\t-M <num> : optimization target [default = %s]\n", nMode ? "area" : "AIG node" );
Abc_Print( -2, "\t-M <num> : optimization target [default = %s]\n", nMode ? "mapped" : "AIG" );
Abc_Print( -2, "\t-A <num> : mapper (0: amap, 1: &nf, 2: &simap) (experimental) [default = %d]\n", nMappedMode );
Abc_Print( -2, "\t-C <file> : AIGER specifying external cares\n");
Abc_Print( -2, "\t-S <num> : the random seed (0: random, >= 1: user defined) [default = %d]\n", nSeed );
Abc_Print( -2, "\t-T <num> : the timeout in seconds (0: unlimited) [default = %d]\n", nTimeOut );
Abc_Print( -2, "\t-V <num> : the verbosity level [default = %d]\n", nVerbose );
Abc_Print( -2, "\t-c : check the equivalence [default = %s]\n", fCheck ? "yes" : "no" );
Abc_Print( -2, "\t-c : check the equivalence [default = %s]\n", fCheck ? "yes" : "no" );
Abc_Print( -2, "\t-d : toggle perform \"dch\" before mapping [default = %s]\n", fDch ? "yes" : "no" );
Abc_Print( -2, "\t-t : toggle timing-driven rewiring [default = %s]\n", fTiming ? "yes" : "no" );
Abc_Print( -2, "\t-h : prints the command usage\n" );
Abc_Print( -2, "\n\tThis command was contributed by Jiun-Hao Chen from National Taiwan University.\n" );
return 1;
Expand Down Expand Up @@ -46755,14 +46763,14 @@ int Abc_CommandAbc9Rrr( Abc_Frame_t * pAbc, int argc, char ** argv )
***********************************************************************/
int Abc_CommandAbc9Rewire( Abc_Frame_t * pAbc, int argc, char ** argv )
{
extern Gia_Man_t *Gia_ManRewire(Gia_Man_t *pGia, Gia_Man_t *pExc, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int nSeed, int fCheck, int fChoices, int fVerbose);
extern Gia_Man_t *Gia_ManRewire(Gia_Man_t *pGia, Gia_Man_t *pExc, int nIters, float levelGrowRatio, int nExpands, int nGrowth, int nDivs, int nFaninMax, int nTimeOut, int nMode, int nMappedMode, int nDist, int fDch, int fTiming, int nSeed, int fCheck, int fChoices, int fVerbose);
FILE *pFile = NULL;
Gia_Man_t *pTemp, *pExc = NULL;
int c, nIters = 100000, nExpands = 128, nGrowth = 4, nDivs = -1, nFaninMax = 8, nSeed = 1, nTimeOut = 0, nVerbose = 1, nMode = 0, nMappedMode = 0, nDist = 0, fCheck = 0, fChoices = 0;
int c, nIters = 100000, nExpands = 128, nGrowth = 4, nDivs = -1, nFaninMax = 8, nSeed = 1, nTimeOut = 0, nVerbose = 1, nMode = 0, nMappedMode = 0, nDist = 0, fCheck = 0, fChoices = 0, fDch = 1, fTiming = 0;
float nLevelGrowRatio = 0;
Extra_UtilGetoptReset();

while ( ( c = Extra_UtilGetopt( argc, argv, "IEGDFSTMALRCVcsh" ) ) != EOF ) {
while ( ( c = Extra_UtilGetopt( argc, argv, "IEGDFSTMALRCVcsdth" ) ) != EOF ) {
switch ( c ) {
case 'I':
if ( globalUtilOptind >= argc )
Expand Down Expand Up @@ -46894,6 +46902,12 @@ int Abc_CommandAbc9Rewire( Abc_Frame_t * pAbc, int argc, char ** argv )
case 's':
fChoices ^= 1;
break;
case 'd':
fDch ^= 1;
break;
case 't':
fTiming ^= 1;
break;
case 'h':
default:
goto usage;
Expand All @@ -46909,13 +46923,13 @@ int Abc_CommandAbc9Rewire( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Print( -1, "Empty GIA network.\n" );
return 1;
}
if ( nMode >= 1 && Abc_FrameReadLibGen2() == NULL )
if ( nMode == 1 && Abc_FrameReadLibGen2() == NULL )
{
Abc_Print( -1, "Library is not available.\n" );
return 1;
}

pTemp = Gia_ManRewire( pAbc->pGia, pExc, nIters, nLevelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, nSeed, fCheck, fChoices, nVerbose );
pTemp = Gia_ManRewire( pAbc->pGia, pExc, nIters, nLevelGrowRatio, nExpands, nGrowth, nDivs, nFaninMax, nTimeOut, nMode, nMappedMode, nDist, fDch, fTiming, nSeed, fCheck, fChoices, nVerbose );
if ( pExc )
Gia_ManStop( pExc );
Abc_FrameUpdateGia( pAbc, pTemp );
Expand All @@ -46931,14 +46945,16 @@ int Abc_CommandAbc9Rewire( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Print( -2, "\t-F <num> : the limit on the fanin count at a node [default = %d]\n", nFaninMax);
Abc_Print( -2, "\t-L <num> : localization distances (0: unlimited) [default = %d]\n", nDist);
Abc_Print( -2, "\t-R <num> : level constraint (0: unlimited, 1: preserve level) [default = %g]\n", nLevelGrowRatio);
Abc_Print( -2, "\t-M <num> : optimization target [default = %s]\n", nMode ? "area" : "AIG node" );
Abc_Print( -2, "\t-M <num> : optimization target [default = %s]\n", nMode ? "mapped" : "aig" );
Abc_Print( -2, "\t-A <num> : mapper (0: amap, 1: &nf, 2: &simap) (experimental) [default = %d]\n", nMappedMode );
Abc_Print( -2, "\t-C <file> : AIGER specifying external cares\n");
Abc_Print( -2, "\t-S <num> : the random seed (0: random, >= 1: user defined) [default = %d]\n", nSeed );
Abc_Print( -2, "\t-T <num> : the timeout in seconds (0: unlimited) [default = %d]\n", nTimeOut );
Abc_Print( -2, "\t-V <num> : the verbosity level [default = %d]\n", nVerbose );
Abc_Print( -2, "\t-c : check the equivalence [default = %s]\n", fCheck ? "yes" : "no" );
Abc_Print( -2, "\t-s : toggle accumulating structural choices [default = %s]\n", fChoices ? "yes" : "no" );
Abc_Print( -2, "\t-c : check the equivalence [default = %s]\n", fCheck ? "yes" : "no" );
Abc_Print( -2, "\t-s : toggle accumulating structural choices [default = %s]\n", fChoices ? "yes" : "no" );
Abc_Print( -2, "\t-d : toggle using \"dch\" before mapping [default = %s]\n", fDch ? "yes" : "no" );
Abc_Print( -2, "\t-t : toggle timing-driven re-wiring [default = %s]\n", fTiming ? "yes" : "no" );
Abc_Print( -2, "\t-h : prints the command usage\n" );
Abc_Print( -2, "\n\tThis command was contributed by Jiun-Hao Chen from National Taiwan University.\n" );
return 1;
Expand Down
4 changes: 2 additions & 2 deletions src/map/mio/mio.c
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Expand Up @@ -77,8 +77,8 @@ static char * pMcncGenlib[] = {
static char * pAndGenlib[] = {
"GATE zero 0 O=CONST0;\n",
"GATE one 0 O=CONST1;\n",
"GATE buf 1 O=a; PIN * NONINV 1 999 1.0 0.0 1.0 0.0\n",
"GATE inv 1 O=!a; PIN * INV 1 999 1.0 0.0 1.0 0.0\n",
"GATE buf 1 O=a; PIN * NONINV 1 999 0.0 0.0 0.0 0.0\n",
"GATE inv 1 O=!a; PIN * INV 1 999 0.0 0.0 0.0 0.0\n",
"GATE and00 1 O=a*b; PIN * NONINV 1 999 1.0 0.0 1.0 0.0\n",
"GATE and01 1 O=a*!b; PIN * NONINV 1 999 1.0 0.0 1.0 0.0\n",
"GATE and10 1 O=!a*b; PIN * NONINV 1 999 1.0 0.0 1.0 0.0\n",
Expand Down
8 changes: 4 additions & 4 deletions src/opt/rar/module.make
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@@ -1,4 +1,4 @@
SRC += src/opt/rar/rewire_rng.c \
src/opt/rar/rewire_map.c \
src/opt/rar/rewire_rar.c \
src/opt/rar/rewire_miaig.cpp
SRC += src/opt/rar/rewireRng.c \
src/opt/rar/rewireMap.c \
src/opt/rar/rewireRar.c \
src/opt/rar/rewireMiaig.cpp
30 changes: 27 additions & 3 deletions src/opt/rar/rewire_map.c → src/opt/rar/rewireMap.c
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/**CFile****************************************************************

FileName [rewire_map.c]
FileName [rewireMap.c]

SystemName [ABC: Logic synthesis and verification system.]

Expand All @@ -14,16 +14,17 @@

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [$Id: rewire_map.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
Revision [$Id: rewireMap.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]

***********************************************************************/

#include "rewire_map.h"
#include "rewireMap.h"

ABC_NAMESPACE_IMPL_START

extern Abc_Ntk_t *Abc_NtkFromAigPhase(Aig_Man_t *pMan);
extern Abc_Ntk_t *Abc_NtkDarAmap(Abc_Ntk_t *pNtk, Amap_Par_t *pPars);
extern Abc_Ntk_t * Abc_NtkDch( Abc_Ntk_t * pNtk, Dch_Pars_t * pPars );
extern void *Abc_FrameReadLibGen2();
extern Vec_Int_t * Abc_NtkWriteMiniMapping( Abc_Ntk_t * pNtk );
extern void Abc_NtkPrintMiniMapping( int * pArray );
Expand All @@ -43,6 +44,28 @@ Abc_Ntk_t *Gia_ManRewirePut(Gia_Man_t *pGia) {
return pNtk;
}

Abc_Ntk_t *Abc_ManRewireDch(Abc_Ntk_t *pNtk) {
Dch_Pars_t Pars, *pPars = &Pars;
Dch_ManSetDefaultParams(pPars);
pNtk = Abc_NtkDch(pNtk, pPars);
if (pNtk == NULL) {
Abc_Print(-1, "Dch compute has failed.\n");
return NULL;
}
return pNtk;
}

Gia_Man_t *Gia_ManRewireDch(Gia_Man_t *pGia) {
Dch_Pars_t Pars, *pPars = &Pars;
Dch_ManSetDefaultParams(pPars);
pGia = Gia_ManPerformDch( pGia, pPars );
if (pGia == NULL) {
Abc_Print(-1, "Dch compute has failed.\n");
return NULL;
}
return pGia;
}

Abc_Ntk_t *Abc_ManRewireMapAmap(Abc_Ntk_t *pNtk) {
Amap_Par_t Pars, *pPars = &Pars;
Amap_ManSetDefaultParams(pPars);
Expand All @@ -67,6 +90,7 @@ Abc_Ntk_t *Gia_ManRewireMapNf(Gia_Man_t *pGia) {
}

Abc_Ntk_t *Gia_ManRewireMapSimap(Gia_Man_t *pGia, int nBound, int nBTLimit, int nTimeout) {
Abc_Print(-1, "[Warning] Gia_ManRewireMapSimap is SAT-based experimental mode.\n");
if (!Gia_ManSimpleMapping(pGia, nBound, 0, nBTLimit, nTimeout, 0, 0, 0, NULL)) {
// Abc_Print(-1, "Mapping has failed.\n");
return NULL;
Expand Down
7 changes: 5 additions & 2 deletions src/opt/rar/rewire_map.h → src/opt/rar/rewireMap.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/**CFile****************************************************************

FileName [rewire_map.h]
FileName [rewireMap.h]

SystemName [ABC: Logic synthesis and verification system.]

Expand All @@ -14,7 +14,7 @@

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [$Id: rewire_map.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
Revision [$Id: rewireMap.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]

***********************************************************************/

Expand All @@ -24,12 +24,15 @@
#include "base/abc/abc.h"
#include "aig/gia/giaAig.h"
#include "map/amap/amap.h"
#include "proof/dch/dch.h"
#include "map/mio/mio.h"
#include "aig/miniaig/miniaig.h"

ABC_NAMESPACE_HEADER_START

Abc_Ntk_t *Gia_ManRewirePut(Gia_Man_t *pGia);
Abc_Ntk_t *Abc_ManRewireDch(Abc_Ntk_t *pNtk);
Gia_Man_t *Gia_ManRewireDch(Gia_Man_t *pGia);
Abc_Ntk_t *Abc_ManRewireMapAmap(Abc_Ntk_t *pNtk);
Abc_Ntk_t *Gia_ManRewireMapNf(Gia_Man_t *pGia);
Abc_Ntk_t *Gia_ManRewireMapSimap(Gia_Man_t *pGia, int nBound, int nBTLimit, int nTimeout);
Expand Down
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