SPI-Protocol-Implementation-in-Verilog

this project explores the implementation and testing of the transfer of data serially between a Master/Slave or smart/dumb devices configuration

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
SPI.sv		SPI.sv
SPI_Cont.sv		SPI_Cont.sv
SPI_Periph.sv		SPI_Periph.sv
SPI_TB.sv		SPI_TB.sv
spi_Master.v		spi_Master.v
spi_slave.v		spi_slave.v
testbench.v		testbench.v

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