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emebemeb
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stm32h7rs: fix formatting issues found by CI
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‎src/target/stm32h7rs.c‎

Lines changed: 93 additions & 100 deletions
Original file line numberDiff line numberDiff line change
@@ -35,91 +35,91 @@
3535
#include "stm32_common.h"
3636

3737
/* Flash Program and Erase Controller Register Map */
38-
#define FPEC1_BASE 0x52002000U
39-
#define FLASH_ACR 0x000U
40-
#define FLASH_KEYR 0x004U
41-
#define FLASH_CR 0x010U
42-
#define FLASH_SR 0x014U
43-
#define FLASH_IER 0x020U
44-
#define FLASH_ISR 0x024U
45-
#define FLASH_ICR 0x028U
46-
#define FLASH_CRCCR 0x030U
47-
#define FLASH_CRCDATA 0x03cU
48-
#define FLASH_SR_BSY (1U << 0U)
49-
#define FLASH_SR_WBNE (1U << 1U)
50-
#define FLASH_SR_QW (1U << 2U)
51-
#define FLASH_SR_CRC_BUSY (1U << 3U)
52-
#define FLASH_ISR_EOP (1U << 16U)
53-
#define FLASH_ISR_WRPERR (1U << 17U)
54-
#define FLASH_ISR_PGSERR (1U << 18U)
55-
#define FLASH_ISR_STRBERR (1U << 19U)
56-
#define FLASH_ISR_INCERR (1U << 21U)
57-
#define FLASH_ISR_RDSERR (1U << 24U)
58-
#define FLASH_ISR_SNECCERR (1U << 25U)
59-
#define FLASH_ISR_DBECCERR (1U << 26U)
60-
#define FLASH_ISR_CRCEND (1U << 27U)
61-
#define FLASH_ISR_CRCRDERR (1U << 28U)
62-
#define FLASH_ISR_ERROR_READ (FLASH_ISR_RDSERR | FLASH_ISR_SNECCERR | FLASH_ISR_DBECCERR)
63-
#define FLASH_ISR_ERROR_MASK \
38+
#define FPEC1_BASE 0x52002000U
39+
#define FLASH_ACR 0x000U
40+
#define FLASH_KEYR 0x004U
41+
#define FLASH_CR 0x010U
42+
#define FLASH_SR 0x014U
43+
#define FLASH_IER 0x020U
44+
#define FLASH_ISR 0x024U
45+
#define FLASH_ICR 0x028U
46+
#define FLASH_CRCCR 0x030U
47+
#define FLASH_CRCDATA 0x03cU
48+
#define FLASH_SR_BSY (1U << 0U)
49+
#define FLASH_SR_WBNE (1U << 1U)
50+
#define FLASH_SR_QW (1U << 2U)
51+
#define FLASH_SR_CRC_BUSY (1U << 3U)
52+
#define FLASH_ISR_EOP (1U << 16U)
53+
#define FLASH_ISR_WRPERR (1U << 17U)
54+
#define FLASH_ISR_PGSERR (1U << 18U)
55+
#define FLASH_ISR_STRBERR (1U << 19U)
56+
#define FLASH_ISR_INCERR (1U << 21U)
57+
#define FLASH_ISR_RDSERR (1U << 24U)
58+
#define FLASH_ISR_SNECCERR (1U << 25U)
59+
#define FLASH_ISR_DBECCERR (1U << 26U)
60+
#define FLASH_ISR_CRCEND (1U << 27U)
61+
#define FLASH_ISR_CRCRDERR (1U << 28U)
62+
#define FLASH_ISR_ERROR_READ (FLASH_ISR_RDSERR | FLASH_ISR_SNECCERR | FLASH_ISR_DBECCERR)
63+
#define FLASH_ISR_ERROR_MASK \
6464
(FLASH_ISR_WRPERR | FLASH_ISR_PGSERR | FLASH_ISR_STRBERR | FLASH_ISR_INCERR | FLASH_ISR_ERROR_READ)
65-
#define FLASH_CR_LOCK (1U << 0U)
66-
#define FLASH_CR_PG (1U << 1U)
67-
#define FLASH_CR_SER (1U << 2U)
68-
#define FLASH_CR_BER (1U << 3U)
69-
#define FLASH_CR_FW (1U << 4U)
70-
#define FLASH_CR_START (1U << 5U)
71-
#define FLASH_CR_SSN_SHIFT 6U
72-
#define FLASH_CR_CRC_EN (1U << 17U)
73-
#define FLASH_CRCCR_ALL_BANK (1U << 7U)
74-
#define FLASH_CRCCR_START_CRC (1U << 16U)
75-
#define FLASH_CRCCR_CLEAN_CRC (1U << 17U)
76-
#define FLASH_CRCCR_CRC_BURST_3 (3U << 20U)
77-
78-
#define STM32H7RS_FLASH_KEY1 0x45670123U
79-
#define STM32H7RS_FLASH_KEY2 0xcdef89abU
80-
81-
#define STM32H7RS_OPT_KEY1 0x08192a3bU
82-
#define STM32H7RS_OPT_KEY2 0x4c5d6e7fU
83-
84-
#define STM32H7RS_FLASH_SIZE 0x1ff1e880U
85-
#define STM32H7RS_FLASH_BANK1_BASE 0x08000000U
86-
#define STM32H7RS_FLASH_BANK_SIZE 0x00010000U
87-
#define NUM_SECTOR_PER_BANK 8U
88-
#define FLASH_SECTOR_SIZE 0x2000U
65+
#define FLASH_CR_LOCK (1U << 0U)
66+
#define FLASH_CR_PG (1U << 1U)
67+
#define FLASH_CR_SER (1U << 2U)
68+
#define FLASH_CR_BER (1U << 3U)
69+
#define FLASH_CR_FW (1U << 4U)
70+
#define FLASH_CR_START (1U << 5U)
71+
#define FLASH_CR_SSN_SHIFT 6U
72+
#define FLASH_CR_CRC_EN (1U << 17U)
73+
#define FLASH_CRCCR_ALL_BANK (1U << 7U)
74+
#define FLASH_CRCCR_START_CRC (1U << 16U)
75+
#define FLASH_CRCCR_CLEAN_CRC (1U << 17U)
76+
#define FLASH_CRCCR_CRC_BURST_3 (3U << 20U)
77+
78+
#define STM32H7RS_FLASH_KEY1 0x45670123U
79+
#define STM32H7RS_FLASH_KEY2 0xcdef89abU
80+
81+
#define STM32H7RS_OPT_KEY1 0x08192a3bU
82+
#define STM32H7RS_OPT_KEY2 0x4c5d6e7fU
83+
84+
#define STM32H7RS_FLASH_SIZE 0x1ff1e880U
85+
#define STM32H7RS_FLASH_BANK1_BASE 0x08000000U
86+
#define STM32H7RS_FLASH_BANK_SIZE 0x00010000U
87+
#define NUM_SECTOR_PER_BANK 8U
88+
#define FLASH_SECTOR_SIZE 0x2000U
8989

9090
/* WWDG base address and register map */
91-
#define STM32H7RS_WWDG_BASE 0x40002c00U
92-
#define STM32H7RS_WWDG_CR (STM32H7RS_WWDG_BASE + 0x00)
93-
#define STM32H7RS_WWDG_CR_RESET 0x0000007fU
91+
#define STM32H7RS_WWDG_BASE 0x40002c00U
92+
#define STM32H7RS_WWDG_CR (STM32H7RS_WWDG_BASE + 0x00)
93+
#define STM32H7RS_WWDG_CR_RESET 0x0000007fU
9494

9595
/* IWDG base address and register map */
96-
#define STM32H7RS_IWDG_BASE 0x58004800U
97-
#define STM32H7RS_IWDG_KEY (STM32H7RS_IWDG_BASE + 0x00U)
98-
#define STM32H7RS_IWDG_KEY_RESET 0x0000aaaaU
96+
#define STM32H7RS_IWDG_BASE 0x58004800U
97+
#define STM32H7RS_IWDG_KEY (STM32H7RS_IWDG_BASE + 0x00U)
98+
#define STM32H7RS_IWDG_KEY_RESET 0x0000aaaaU
9999

100100
/*
101101
* Access from processor address space.
102102
* Access via the APB-D is at 0xe00e1000
103103
*/
104-
#define DBGMCU_IDCODE 0x5c001000U
105-
#define DBGMCU_IDC (DBGMCU_IDCODE + 0U)
106-
#define DBGMCU_CR (DBGMCU_IDCODE + 4U)
107-
#define DBGMCU_APB1FREEZE (DBGMCU_IDCODE + 0x03cU)
108-
#define DBGMCU_APB4FREEZE (DBGMCU_IDCODE + 0x054U)
109-
#define DBGSLEEP_D1 (1U << 0U)
110-
#define DBGSTOP_D1 (1U << 1U)
111-
#define DBGSTBY_D1 (1U << 2U)
112-
#define DBGSTOP_D3 (1U << 7U)
113-
#define DBGSTBY_D3 (1U << 8U)
114-
#define D1DBGCKEN (1U << 21U)
115-
#define D3DBGCKEN (1U << 22U)
116-
#define DBGMCU_APB1FREEZE_WWDG1 (1U << 11U)
117-
#define DBGMCU_APB4FREEZE_IWDG1 (1U << 18U)
118-
119-
#define STM32H7RS_DBGMCU_IDCODE_DEV_MASK 0x00000fffU
120-
#define STM32H7RS_DBGMCU_IDCODE_REV_SHIFT 16U
121-
122-
#define ID_STM32H7RS 0x485U /* RM0477 */
104+
#define DBGMCU_IDCODE 0x5c001000U
105+
#define DBGMCU_IDC (DBGMCU_IDCODE + 0U)
106+
#define DBGMCU_CR (DBGMCU_IDCODE + 4U)
107+
#define DBGMCU_APB1FREEZE (DBGMCU_IDCODE + 0x03cU)
108+
#define DBGMCU_APB4FREEZE (DBGMCU_IDCODE + 0x054U)
109+
#define DBGSLEEP_D1 (1U << 0U)
110+
#define DBGSTOP_D1 (1U << 1U)
111+
#define DBGSTBY_D1 (1U << 2U)
112+
#define DBGSTOP_D3 (1U << 7U)
113+
#define DBGSTBY_D3 (1U << 8U)
114+
#define D1DBGCKEN (1U << 21U)
115+
#define D3DBGCKEN (1U << 22U)
116+
#define DBGMCU_APB1FREEZE_WWDG1 (1U << 11U)
117+
#define DBGMCU_APB4FREEZE_IWDG1 (1U << 18U)
118+
119+
#define STM32H7RS_DBGMCU_IDCODE_DEV_MASK 0x00000fffU
120+
#define STM32H7RS_DBGMCU_IDCODE_REV_SHIFT 16U
121+
122+
#define ID_STM32H7RS 0x485U /* RM0477 */
123123

124124
/*
125125
* Uncomment this to enable DBGMCU setup in attach() and detach()
@@ -187,9 +187,9 @@ bool stm32h7rs_probe(target_s *target)
187187
const adiv5_access_port_s *const ap = cortex_ap(target);
188188
if (ap->partno != ID_STM32H7RS)
189189
return false;
190-
190+
191191
target->part_id = ap->partno;
192-
192+
193193
/* Save private storage */
194194
stm32h7rs_priv_s *priv = calloc(1, sizeof(*priv));
195195
if (!priv) { /* calloc failed: heap exhaustion */
@@ -198,13 +198,13 @@ bool stm32h7rs_probe(target_s *target)
198198
}
199199
target->target_storage = priv;
200200
priv->dbg_cr = target_mem32_read32(target, DBGMCU_CR);
201-
201+
202202
target->driver = "STM32H7R/S";
203203
target->attach = stm32h7rs_attach;
204204
target->detach = stm32h7rs_detach;
205205
target->mass_erase = stm32h7rs_mass_erase;
206206
target_add_commands(target, stm32h7rs_cmd_list, target->driver);
207-
207+
208208
/* Now we have a stable debug environment, make sure the WDTs can't bonk the processor out from under us */
209209
target_mem32_write32(target, DBGMCU_APB1FREEZE, DBGMCU_APB1FREEZE_WWDG1);
210210
target_mem32_write32(target, DBGMCU_APB4FREEZE, DBGMCU_APB4FREEZE_IWDG1);
@@ -213,12 +213,10 @@ bool stm32h7rs_probe(target_s *target)
213213
* debugging through sleep, stop and standby states for domain D1
214214
*/
215215
target_mem32_write32(target, DBGMCU_CR,
216-
target_mem32_read32(target, DBGMCU_CR) | DBGSLEEP_D1 |
217-
DBGSTOP_D1 | DBGSTBY_D1 | D1DBGCKEN | D3DBGCKEN);
216+
target_mem32_read32(target, DBGMCU_CR) | DBGSLEEP_D1 | DBGSTOP_D1 | DBGSTBY_D1 | D1DBGCKEN | D3DBGCKEN);
218217
target_mem32_write32(target, STM32H7RS_WWDG_CR, STM32H7RS_WWDG_CR_RESET);
219218
target_mem32_write32(target, STM32H7RS_IWDG_KEY, STM32H7RS_IWDG_KEY_RESET);
220219

221-
222220
/* Build the RAM map */
223221
switch (target->part_id) {
224222
case ID_STM32H7RS: {
@@ -259,8 +257,7 @@ static bool stm32h7rs_attach(target_s *target)
259257
* Make sure that both domain D1 and D3 debugging are enabled and that we can keep
260258
* debugging through sleep, stop and standby states for domain D1 - this is duplicated as it's undone by detach.
261259
*/
262-
target_mem32_write32(target, DBGMCU_CR,
263-
DBGSLEEP_D1 | DBGSTOP_D1 | DBGSTBY_D1 | D1DBGCKEN | D3DBGCKEN);
260+
target_mem32_write32(target, DBGMCU_CR, DBGSLEEP_D1 | DBGSTOP_D1 | DBGSTBY_D1 | D1DBGCKEN | D3DBGCKEN);
264261
target_mem32_write32(target, STM32H7RS_WWDG_CR, STM32H7RS_WWDG_CR_RESET);
265262
target_mem32_write32(target, STM32H7RS_IWDG_KEY, STM32H7RS_IWDG_KEY_RESET);
266263
#endif
@@ -274,8 +271,7 @@ static void stm32h7rs_detach(target_s *target)
274271
* undo DBGMCU setup done in attach()
275272
*/
276273
target_mem32_write32(target, DBGMCU_CR,
277-
target_mem32_read32(target, DBGMCU_CR) &
278-
~(DBGSLEEP_D1 | DBGSTOP_D1 | DBGSTBY_D1 | D1DBGCKEN | D3DBGCKEN));
274+
target_mem32_read32(target, DBGMCU_CR) & ~(DBGSLEEP_D1 | DBGSTOP_D1 | DBGSTBY_D1 | D1DBGCKEN | D3DBGCKEN));
279275
#endif
280276
cortexm_detach(target);
281277
}
@@ -297,8 +293,7 @@ static bool stm32h7rs_flash_wait_complete(target_s *const target, const uint32_t
297293
/* Now the operation's complete, we can check the error bits */
298294
if (istatus & FLASH_ISR_ERROR_MASK)
299295
DEBUG_ERROR("%s: Flash error: %08" PRIx32 "\n", __func__, istatus);
300-
target_mem32_write32(target, regbase + FLASH_ICR,
301-
istatus & (FLASH_ISR_EOP | FLASH_ISR_ERROR_MASK));
296+
target_mem32_write32(target, regbase + FLASH_ICR, istatus & (FLASH_ISR_EOP | FLASH_ISR_ERROR_MASK));
302297
/* Return whether any errors occured */
303298
return !(istatus & FLASH_ISR_ERROR_MASK);
304299
}
@@ -307,12 +302,11 @@ static bool stm32h7rs_flash_unlock(target_s *const target, const uint32_t regbas
307302
{
308303
/* clear any pending flash interrupts that could hurt us */
309304
uint32_t istatus = target_mem32_read32(target, FPEC1_BASE + FLASH_ISR);
310-
if (istatus & FLASH_ISR_ERROR_MASK)
311-
{
305+
if (istatus & FLASH_ISR_ERROR_MASK) {
312306
DEBUG_INFO("%s: FLASH_ISR %08" PRIx32 " - clearing\n", __func__, istatus);
313307
target_mem32_write32(target, FPEC1_BASE + FLASH_ICR, istatus & FLASH_ISR_ERROR_MASK);
314308
}
315-
309+
316310
/* Read out the Flash status and tend to any pending conditions */
317311
const uint32_t status = target_mem32_read32(target, regbase + FLASH_SR);
318312
/* Start by checking if there are any pending ongoing operations */
@@ -321,7 +315,7 @@ static bool stm32h7rs_flash_unlock(target_s *const target, const uint32_t regbas
321315
if (!stm32h7rs_flash_wait_complete(target, regbase))
322316
return false;
323317
}
324-
318+
325319
/* Unlock the device Flash if not already unlocked (it's an error to re-key the controller if it is) */
326320
if (target_mem32_read32(target, regbase + FLASH_CR) & FLASH_CR_LOCK) {
327321
/* Enable Flash controller access */
@@ -352,7 +346,7 @@ static bool stm32h7rs_flash_done(target_flash_s *const target_flash)
352346

353347
static bool stm32h7rs_flash_erase(target_flash_s *const target_flash, target_addr_t addr, const size_t len)
354348
{
355-
(void) len;
349+
(void)len;
356350
/* Erases are always done one sector at a time - the target Flash API guarantees this */
357351
target_s *target = target_flash->t;
358352
const stm32h7rs_flash_s *const flash = (stm32h7rs_flash_s *)target_flash;
@@ -375,7 +369,7 @@ static bool stm32h7rs_flash_write(
375369
target_flash_s *const target_flash, const target_addr_t dest, const void *const src, const size_t len)
376370
{
377371
target_s *target = target_flash->t;
378-
const stm32h7rs_flash_s *const flash = (stm32h7rs_flash_s *)target_flash;
372+
const stm32h7rs_flash_s *const flash = (stm32h7rs_flash_s *)target_flash;
379373

380374
/* Prepare the Flash write operation */
381375
const uint32_t ctrl_pg = FLASH_CR_PG;
@@ -392,7 +386,7 @@ static bool stm32h7rs_flash_write(
392386
*/
393387
if (amount < 16U)
394388
target_mem32_write32(target, flash->regbase + FLASH_CR, ctrl_pg | FLASH_CR_FW);
395-
389+
396390
/* wait for QW bit to clear */
397391
while (target_mem32_read32(target, flash->regbase + FLASH_SR) & FLASH_SR_QW)
398392
continue;
@@ -402,8 +396,7 @@ static bool stm32h7rs_flash_write(
402396
return stm32h7rs_flash_wait_complete(target, flash->regbase);
403397
}
404398

405-
static bool stm32h7rs_erase_bank(
406-
target_s *const target, const uint32_t reg_base)
399+
static bool stm32h7rs_erase_bank(target_s *const target, const uint32_t reg_base)
407400
{
408401
if (!stm32h7rs_flash_unlock(target, reg_base)) {
409402
DEBUG_ERROR("Bank erase: Unlock bank failed\n");
@@ -416,7 +409,8 @@ static bool stm32h7rs_erase_bank(
416409
return true;
417410
}
418411

419-
static bool stm32h7rs_wait_erase_bank(target_s *const target, platform_timeout_s *const timeout, const uint32_t reg_base)
412+
static bool stm32h7rs_wait_erase_bank(
413+
target_s *const target, platform_timeout_s *const timeout, const uint32_t reg_base)
420414
{
421415
while (target_mem32_read32(target, reg_base + FLASH_SR) & FLASH_SR_QW) {
422416
if (target_check_error(target)) {
@@ -465,8 +459,7 @@ static bool stm32h7rs_crc_bank(target_s *target)
465459
return false;
466460

467461
target_mem32_write32(target, reg_base + FLASH_CR, FLASH_CR_CRC_EN);
468-
const uint32_t crc_ctrl =
469-
FLASH_CRCCR_CLEAN_CRC | FLASH_CRCCR_CRC_BURST_3 | FLASH_CRCCR_ALL_BANK;
462+
const uint32_t crc_ctrl = FLASH_CRCCR_CLEAN_CRC | FLASH_CRCCR_CRC_BURST_3 | FLASH_CRCCR_ALL_BANK;
470463
target_mem32_write32(target, reg_base + FLASH_CRCCR, crc_ctrl | FLASH_CRCCR_START_CRC);
471464
uint32_t status = FLASH_SR_CRC_BUSY;
472465
while (status & FLASH_SR_CRC_BUSY) {

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