fix python formatting

Author: builderdev212

.github/workflows/black.yml

@@ -1,4 +1,4 @@
-name: python-black
+name: black
 on: [push, pull_request]
 jobs:
   linter_name:

problems/verilog-language/basics/multi-wire/tb/multi_wire.py

@@ -61,4 +61,4 @@ async def is_equal_check(self):
         if int(self.z.value) != int(self.c.value):
             raise DataError(
                 f"z and c should be equal, but {self.z.value} != {self.c.value}."
-            )
+            )

problems/verilog-language/basics/multi-wire/tb/test_multi_wire.py

@@ -19,7 +19,7 @@ async def output_stays_equal(dut):
     ]
 
     tb.log.info("Checking output value...")
-    
+
     for i in range(len(test_vals)):
         tb.set_input_vals(test_vals[i])
         tb.is_equal_check()

problems/verilog-language/basics/simple-wire/tb/simple_wire.py

@@ -36,4 +36,4 @@ async def is_equal_check(self):
         if int(self.i.value) != int(self.o.value):
             raise DataError(
                 f"Output should be equal, but {self.i.value} != {self.o.value}."
-            )
+            )

problems/verilog-language/basics/simple-wire/tb/test_simple_wire.py

@@ -14,7 +14,7 @@ async def output_stays_equal(dut):
     test_vals = [0, 1, 1, 0, 1, 0]
 
     tb.log.info("Checking output value...")
-    
+
     for i in range(len(test_vals)):
         tb.set_input_val(test_vals[i])
         tb.is_equal_check()