add vector hdl

Author: builderdev212

problems/verilog-language/vectors/four-input-gates/rtl/four_input_gates.v

@@ -0,0 +1,16 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module four_input_gates ( 
+    input  wire [3:0] i,
+    output wire       out_and,
+    output wire       out_or,
+    output wire       out_xor
+);
+    
+    assign out_and = & i;
+    assign out_or = | i;
+    assign out_xor = ^ i;
+
+endmodule

problems/verilog-language/vectors/vector-basics/rtl/vector_basics.v

@@ -0,0 +1,16 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module vector_basics ( 
+    input  wire [2:0] vec,
+    output wire [2:0] outv,
+    output wire       o2,
+    output wire       o1,
+    output wire       o0
+);
+
+    assign outv = vec;
+    assign {o2, o1, o0} = vec;
+    
+endmodule

problems/verilog-language/vectors/vector-bit-replication/rtl/bit_replication.v

@@ -0,0 +1,12 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module bit_replication (
+    input  wire [7:0] i,
+    output wire [31:0] o
+);
+
+    assign o = {{24{i[7]}}, i};
+
+endmodule

problems/verilog-language/vectors/vector-byte-endian-swap/rtl/byte_endian_swap.v

@@ -0,0 +1,20 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module byte_endian_swap #(
+    parameter BYTE_COUNT = 4,
+    parameter BYTE_SIZE = 8
+)( 
+    input  wire [(BYTE_COUNT*BYTE_SIZE)-1:0] i,
+    output wire [(BYTE_COUNT*BYTE_SIZE)-1:0] o
+);
+    
+    genvar i;
+    generate
+        for (i = 0; i < BYTE_COUNT; i++) begin : OUTPUT_ASSIGNMENT
+        	assign o[(BYTE_SIZE*(BYTE_COUNT-i))-1:(BYTE_SIZE*(BYTE_COUNT-1-i))] = i[(BYTE_SIZE*(1+i))-1:BYTE_SIZE*i];
+    	end
+    endgenerate
+
+endmodule

problems/verilog-language/vectors/vector-concatenation/rtl/concatenation.v

@@ -0,0 +1,21 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module concatenation (
+    input  wire [4:0] a,
+    input  wire [4:0] b,
+    input  wire [4:0] c,
+    input  wire [4:0] d,
+    input  wire [4:0] e,
+    input  wire [4:0] f,
+
+    output wire [7:0] w,
+    output wire [7:0] x,
+    output wire [7:0] y,
+    output wire [7:0] z
+);
+
+    assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
+
+endmodule

problems/verilog-language/vectors/vector-gates/rtl/vector_gates.v

@@ -0,0 +1,17 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module vector_gates ( 
+    input  wire [2:0] a,
+    input  wire [2:0] b,
+    output wire [2:0] out_or_bitwise,
+    output wire       out_or_logical,
+    output wire [5:0] out_not
+);
+    
+    assign out_or_bitwise = a | b;
+    assign out_or_logical = a || b;
+    assign out_not = {~b, ~a};
+
+endmodule

problems/verilog-language/vectors/vector-part-select/rtl/vector_splitter.v

@@ -0,0 +1,14 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module vector_splitter ( 
+    input  wire [15:0] i,
+    output wire [7:0]  out_hi,
+    output wire [7:0]  out_lo
+);
+    
+    assign out_hi = i[15:8];
+    assign out_lo = i[7:0];
+
+endmodule

problems/verilog-language/vectors/vector-reverse/rtl/reverse.v

@@ -0,0 +1,19 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module reverse #(
+    parameter VECTOR_SIZE = 8
+)( 
+    input  wire [VECTOR_SIZE-1:0] i,
+    output wire [VECTOR_SIZE-1:0] o
+);
+    
+    genvar i;
+    generate
+        for (i = 0; i < VECTOR_SIZE; i++) begin : INPUT_REVERSE
+            assign out[VECTOR_SIZE-1-i] = in[i];
+        end
+    endgenerate
+
+endmodule

problems/verilog-language/vectors/vector-xnor/rtl/vector_xnor.v

@@ -0,0 +1,16 @@
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+module top_module (
+    input  wire        a,
+    input  wire        b,
+    input  wire        c,
+    input  wire        d,
+    input  wire        e,
+    output wire [24:0] out
+);
+
+    assign out = ~{{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ^ {5{a, b, c, d, e}};
+
+endmodule