review: print the implicit registers as well

Author: abrown

cranelift/assembler-x64/meta/src/generate/format.rs

@@ -14,7 +14,7 @@ impl dsl::Format {
     /// once Cranelift has switched to using this assembler predominantly
     /// (TODO).
     #[must_use]
-    pub fn generate_att_style_operands(&self) -> String {
+    pub(crate) fn generate_att_style_operands(&self) -> String {
         let ordered_ops: Vec<_> = self
             .operands
             .iter()
@@ -25,7 +25,22 @@ impl dsl::Format {
         ordered_ops.join(", ")
     }
 
-    pub fn generate_rex_encoding(&self, f: &mut Formatter, rex: &dsl::Rex) {
+    #[must_use]
+    pub(crate) fn generate_implicit_operands(&self) -> String {
+        let ops: Vec<_> = self
+            .operands
+            .iter()
+            .filter(|o| o.implicit)
+            .map(|o| format!("{{{}}}", o.location))
+            .collect();
+        if ops.is_empty() {
+            String::new()
+        } else {
+            format!(" ;; implicit: {}", ops.join(", "))
+        }
+    }
+
+    pub(crate) fn generate_rex_encoding(&self, f: &mut Formatter, rex: &dsl::Rex) {
         self.generate_prefixes(f, rex);
         self.generate_rex_prefix(f, rex);
         self.generate_opcodes(f, rex);

cranelift/assembler-x64/meta/src/generate/inst.rs

@@ -194,7 +194,7 @@ impl dsl::Inst {
                 f.add_block(
                     "fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result",
                     |f| {
-                        for op in self.format.operands.iter().filter(|o| !o.implicit) {
+                        for op in self.format.operands.iter() {
                             let location = op.location;
                             let to_string = location.generate_to_string(op.extension);
                             fmtln!(f, "let {location} = {to_string};");
@@ -207,7 +207,8 @@ impl dsl::Inst {
                             &self.mnemonic
                         };
                         let ordered_ops = self.format.generate_att_style_operands();
-                        fmtln!(f, "write!(f, \"{inst_name} {ordered_ops}\")");
+                        let implicit_ops = self.format.generate_implicit_operands();
+                        fmtln!(f, "write!(f, \"{inst_name} {ordered_ops}{implicit_ops}\")");
                     },
                 );
             },

cranelift/assembler-x64/src/fuzz.rs

@@ -27,7 +27,7 @@ pub fn roundtrip(inst: &Inst<FuzzRegs>) {
     // off the instruction offset first.
     let expected = expected.split_once(' ').unwrap().1;
     let actual = inst.to_string();
-    if expected != actual && expected != replace_signed_immediates(&actual) {
+    if expected != actual && expected != fix_up(&actual) {
         println!("> {inst}");
         println!("  debug: {inst:x?}");
         println!("  assembled: {}", pretty_print_hexadecimal(&assembled));
@@ -166,6 +166,33 @@ fn replace() {
     );
 }
 
+/// Remove everything after the first semicolon in the disassembly and trim any
+/// trailing spaces. This is necessary to remove the implicit operands we end up
+/// printing for Cranelift's sake.
+fn remove_after_semicolon(dis: &str) -> &str {
+    match dis.find(';') {
+        None => dis,
+        Some(idx) => {
+            let (prefix, _) = dis.split_at(idx);
+            prefix.trim()
+        }
+    }
+}
+
+#[test]
+fn remove_after_parenthesis_test() {
+    assert_eq!(
+        remove_after_semicolon("imulb 0x7658eddd(%rcx) ;; implicit: %ax"),
+        "imulb 0x7658eddd(%rcx)"
+    );
+}
+
+/// Run some post-processing on the disassembly to make it match Capstone.
+fn fix_up(dis: &str) -> std::borrow::Cow<str> {
+    let dis = remove_after_semicolon(dis);
+    replace_signed_immediates(&dis)
+}
+
 /// Fuzz-specific registers.
 ///
 /// For the fuzzer, we do not need any fancy register types; see [`FuzzReg`].

cranelift/filetests/filetests/isa/x64/i128.clif

@@ -207,7 +207,7 @@ block0(v0: i128, v1: i128):
 ;   addq %rsi, %rdx
 ;   movq    %rdi, %rax
 ;   movq    %rdx, %r8
-;   mulq %rcx
+;   mulq %rcx ;; implicit: %rax, %rdx
 ;   movq    %rdx, %rcx
 ;   movq    %r8, %rdx
 ;   addq %rcx, %rdx
@@ -1904,7 +1904,7 @@ block0(v0: i64, v1: i64):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulq %rsi
+;   mulq %rsi ;; implicit: %rax, %rdx
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -1968,7 +1968,7 @@ block0(v0: i64, v1: i64):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulq %rsi
+;   mulq %rsi ;; implicit: %rax, %rdx
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -1997,7 +1997,7 @@ block0(v0: i64, v1: i64):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   imulq %rsi
+;   imulq %rsi ;; implicit: %rax, %rdx
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret

cranelift/filetests/filetests/isa/x64/mul.clif

@@ -13,7 +13,7 @@ block0(v0: i8, v1: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulb %sil
+;   mulb %sil ;; implicit: %ax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -122,8 +122,8 @@ block0(v0: i8, v1: i8, v2: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulb %sil
-;   mulb %dl
+;   mulb %sil ;; implicit: %ax
+;   mulb %dl ;; implicit: %ax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -237,7 +237,7 @@ block0(v0: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulb (%rip)
+;   mulb (%rip) ;; implicit: %ax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -502,7 +502,7 @@ block0(v0: i8, v1: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   imulb %sil
+;   imulb %sil ;; implicit: %ax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -531,7 +531,7 @@ block0(v0: i8, v1: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulb %sil
+;   mulb %sil ;; implicit: %ax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret

cranelift/filetests/filetests/isa/x64/smulhi.clif

@@ -12,7 +12,7 @@ block0(v0: i8, v1: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   imulb %sil
+;   imulb %sil ;; implicit: %ax
 ;   sarw    $8, %ax, %ax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -41,7 +41,7 @@ block0(v0: i16, v1: i16):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   imulw %si
+;   imulw %si ;; implicit: %ax, %dx
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -70,7 +70,7 @@ block0(v0: i32, v1: i32):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   imull %esi
+;   imull %esi ;; implicit: %eax, %edx
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -99,7 +99,7 @@ block0(v0: i64, v1: i64):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   imulq %rsi
+;   imulq %rsi ;; implicit: %rax, %rdx
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp

cranelift/filetests/filetests/isa/x64/umulhi.clif

@@ -12,7 +12,7 @@ block0(v0: i8, v1: i8):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulb %sil
+;   mulb %sil ;; implicit: %ax
 ;   shrw    $8, %ax, %ax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -41,7 +41,7 @@ block0(v0: i16, v1: i16):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulw %si
+;   mulw %si ;; implicit: %ax, %dx
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -70,7 +70,7 @@ block0(v0: i32, v1: i32):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mull %esi
+;   mull %esi ;; implicit: %eax, %edx
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
@@ -99,7 +99,7 @@ block0(v0: i64, v1: i64):
 ;   movq    %rsp, %rbp
 ; block0:
 ;   movq    %rdi, %rax
-;   mulq %rsi
+;   mulq %rsi ;; implicit: %rax, %rdx
 ;   movq    %rdx, %rax
 ;   movq    %rbp, %rsp
 ;   popq    %rbp