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x86: fix access metadata for EVEX writemasks - #3059

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raaller wants to merge 1 commit into
capstone-engine:nextfrom
raaller:fix/x86-avx512-opmask-access
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x86: fix access metadata for EVEX writemasks#3059
raaller wants to merge 1 commit into
capstone-engine:nextfrom
raaller:fix/x86-avx512-opmask-access

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@raaller

@raaller raaller commented Sep 1, 2026

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Your checklist for this pull request

  • I've documented or updated the documentation of every API function and struct this PR changes.
  • I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

EVEX writemasks are exposed by the x86 printers as additional "cs_x86_op" operands, while the instruction access table describes only the non-writemask semantic operands. Using the public operand position directly therefore shifts the access lookup.

With Intel syntax, operands after the writemask can lose their access metadata. With AT&T syntax, the writemask itself is appended after the semantic operands and receives no access metadata. This change records the operand created from "ENCODING_WRITEMASK" and its corresponding detail-operand position. The printers assign "CS_AC_READ" to that operand and exclude it from the semantic access index. K registers used as regular instruction operands are left unchanged.

Test plan

Added seven regression tests covering:

  • Intel and AT&T syntax;
  • zeroing and merging masks;
  • register and memory sources;
  • an unmasked control case;
  • a second masked opcode ("VMOVDQU64");
  • an instruction with an immediate operand ("VPSLLD").

Closing issues

Closes #2565

@github-actions github-actions Bot added X86 Arch LLVM-core-files auto-sync labels Sep 1, 2026
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AVX512 Masked instruction cause last register to not have an "ACCESS" mode.

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