Adding RISCV to supported architectures - #83

Merged

Rot127 merged 9 commits into

capstone-engine:auto-sync-18from

moste00:riscv_support

Jan 25, 2026

Commits on Jul 17, 2025

Added RISCV to supported architectures and added code to recognize its immediate operands
moste00
committed
e41b4b2

Commits on Jul 26, 2025

added support for primary key index generation and other fixes
moste00
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ca565fc

Commits on Aug 23, 2025

added compressed instruction info generation and the necessary fixes
moste00
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974f448

Commits on Sep 5, 2025

final touches to fix the generation of compressed instruction info logic
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2bfe659

Commits on Oct 21, 2025

added isCall flag and generated MEM access for some instructions with missing MEM
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5cbcec6

Commits on Oct 22, 2025

[BACKPATCH] fixed problem with c_srli immediates by cherry picking a fix from upstream, REMOVE WHEN REBASING ON TOP OF 20.0
moste00
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72ca092

Commits on Dec 23, 2025

revert bad isCall flag setting
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ffdfb99

Commits on Jan 8, 2026

use llvm regex instead of C++ stdlib regex, various cleanups and review comment addressing
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95db779

Commits on Jan 18, 2026

revert extraneous formatting
moste00
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59d548d