PowerPC: add mcrxr instruction definition - #94
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mcrxr (Move to Condition Register from XER) was part of the original POWER/PowerPC architecture, but was dropped from Book I as of PowerPC ISA 2.03 - superseded by the non-destructive mcrxrx below on ISA 3.0+ implementations. It moves the top 4 XER bits (SO, OV, CA and a reserved bit) into a chosen CR field and clears them in XER. It's still found in legacy PowerPC/POWER binaries, but was never implemented by LLVM's own PPC backend (which post-dates its removal from the ISA), so it isn't decoded by Capstone either. Encoding is X-form, opcode 31, XO 512 - the same XForm_17-derived layout already used above for mcrxrx's XO 576, with the same single BF (crf) operand. That XO slot is unused by any other PPC instruction, so it's added unconditionally, without a Requires<> predicate. Added a matching P9/P10 scheduling-resource entry (mirroring mcrxrx's) in P9InstrResources.td / P10InstrResources.td: both processor models have CompleteModel = 1, so mcrxr needs a scheduling class to keep tblgen's schedule-completeness check passing. This is the counterpart to capstone-engine/capstone#3065, which carries the corresponding regenerated Capstone tables (regenerated via ASUpdater -a PPC against this change) and has the verification details (test suite results, encoding confirmation, etc). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012jWces2QBvBWg9m3NfxH4v
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Implements the
mcrxropcode for disassembly (Move to Condition Register from XER). This opcode was part of the original POWER/PowerPC architecture but was dropped from Book I as of PowerPC ISA 2.03.This CL backs capstone-engine/capstone#3065 (with issue capstone-engine/capstone#3066).
Tests and all PPC table generators complete without error.