Merge pull request #33 from mchirindo/devel_3

Red Pitaya sys_block default parameters

Author: wnew

jasper_library/hdl_sources/sys_block/counter.v

@@ -0,0 +1,55 @@
+//============================================================================//
+//                                                                            //
+//      Parameterize Counter                                                  //
+//                                                                            //
+//      Module name: counter                                                  //
+//      Desc: parameterized counter, counts up/down in any increment          //
+//      Date: Oct 2011                                                        //
+//      Developer: Rurik Primiani & Wesley New                                //
+//      Adapted by: Mathews Chirindo                                          //
+//      Date: Jan 2020                                                        //
+//      Licence: GNU General Public License ver 3                             //
+//      Notes:                                                                //
+//                                                                            //
+//============================================================================//
+
+module counter #(
+      //==============================
+      // Top level block parameters
+      //==============================
+      parameter DATA_WIDTH   = 32,               // number of bits in counters
+      parameter COUNT_FROM   = 0,               // start with this number
+      parameter COUNT_TO     = 2**(DATA_WIDTH), // value to count to in CL case
+      parameter STEP         = 1                // negative or positive, sets direction
+   ) (
+      //===============
+      // Input Ports
+      //===============
+      input user_clk,
+      input en,
+      input user_rst,
+
+      //===============
+      // Output Ports
+      //===============
+      output reg [DATA_WIDTH-1:0] count_out,
+      output we
+   );
+   
+   assign we = 1'b1;
+   
+// Synchronous logic
+   always @(posedge user_clk) begin
+      // if ACTIVE_LOW_RST is defined then reset on a low
+      // this should be defined on a system-wide basis
+       if (`ifdef ACTIVE_LOW_RST user_rst `else !user_rst `endif) begin
+         if (en == 1) begin
+           count_out <= count_out + STEP;
+         end
+       end 
+       else begin
+         count_out <= COUNT_FROM;
+       end // else: if(rst != 0)
+   end
+endmodule
+

jasper_library/toolflow.py

@@ -810,11 +810,12 @@ def generate_xml_memory_map(self, memory_map):
                 # node.set('size', str(reg.nbytes))
                 node.set('permission', reg.mode)               
                 if reg.mode == 'r':
-                    # Basically a To Processor register (status)
-                    node.set('hw_permission', 'w')
-                    # Populate defaults if sys_block version registers
-                    if reg.name == 'sys_board_id' or reg.name == 'sys_rev' or reg.name == 'sys_rev_rcs': 
-                        node.set('hw_rst', str(reg.default_val))
+                    if reg.default_val != 0:
+                       # Populate defaults of sys_block version registers
+                       node.set('hw_rst', str(reg.default_val))
+                    else:
+                       # Basically a To Processor register (status)
+                       node.set('hw_permission', 'w')
                 else:
                     # Only for a From Processor register (control)
                     node.set('hw_rst', str(reg.default_val))

jasper_library/yellow_blocks/red_pitaya.py

@@ -92,7 +92,7 @@ def modify_top(self,top):
 
 
     def gen_children(self):
-        return [YellowBlock.make_block({'tag': 'xps:sys_block', 'board_id': '4', 'rev_maj': '1', 'rev_min': '0', 'rev_rcs': '1'}, self.platform)]
+        return [YellowBlock.make_block({'fullpath': self.fullpath, 'tag': 'xps:sys_block', 'board_id': '4', 'rev_maj': '1', 'rev_min': '0', 'rev_rcs': '1','scratchpad': '0'}, self.platform)]
         # return [YellowBlock.make_block({'tag': 'xps:sys_block', 'board_id': '3', 'rev_maj': '2', 'rev_min': '0', 'rev_rcs': '1'}, self.platform),
         #         YellowBlock.make_block({'tag': 'xps:AXI4LiteInterconnect', 'name': 'AXI4LiteInterconnect'}, self.platform)]
 

jasper_library/yellow_blocks/sys_block.py

@@ -2,22 +2,31 @@
 from memory import Register
 from .yellow_block_typecodes import *
 
+
 class sys_block(YellowBlock):
     def initialize(self):
         self.typecode = TYPECODE_SYSBLOCK
-        self.add_source('sys_block')
+        self.add_source('sys_block')             
         # the internal memory_map
         self.memory_map = [
             Register('sys_board_id',   mode='r',  offset=0, default_val=self.board_id),
             Register('sys_rev',        mode='r',  offset=0x4, default_val=str((int(self.rev_maj) << 16) + int(self.rev_min))),
             Register('sys_rev_rcs',    mode='r',  offset=0xc, default_val=self.rev_rcs),
-            Register('sys_scratchpad', mode='rw', offset=0x10),
+            Register('sys_scratchpad', mode='rw', offset=0x10, default_val=self.scratchpad),
             Register('sys_clkcounter', mode='r',  offset=0x14),
         ]
     def modify_top(self,top):
-        # check for mmbus_architecture (added to bus arch. support for AXI4-Lite)
         if self.platform.mmbus_architecture == 'AXI4-Lite':
-            top.add_axi4lite_interface('sys_block', mode='r', nbytes=32, memory_map=self.memory_map, typecode=self.typecode)
+            inst = top.get_instance('counter', 'counter_inst')          
+            inst.add_parameter('DATA_WIDTH', 32)
+            inst.add_port('user_clk', 'user_clk')
+            inst.add_port('user_rst', 'user_rst')
+            inst.add_port('en', '1')           
+            design_name = self.fullname.replace("_"+self.fullpath, "")
+            inst.add_port('we',  signal='%s_sys_clkcounter_we' % design_name, dir='out', width=1)
+            inst.add_port('count_out', signal='%s_sys_clkcounter_in' % design_name, dir='out', width=32)
+            top.add_axi4lite_interface('sys_block', mode='r', nbytes=32, memory_map=self.memory_map, typecode=self.typecode)                    
+
         else:
             inst = top.get_instance('sys_block', 'sys_block_inst')
             inst.add_parameter('BOARD_ID', self.board_id)
@@ -26,4 +35,4 @@ def modify_top(self,top):
             inst.add_parameter('REV_RCS', self.rev_rcs)
             inst.add_port('user_clk', 'user_clk', parent_port=False, parent_sig=False)
             inst.add_wb_interface('sys_block', mode='r', nbytes=32, memory_map=self.memory_map, typecode=self.typecode)
-        
+