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jack-hjack-h
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Merge pull request #123 from ska-sa/devel
Asymmetric BRAM and Red Pitaya compile Fixes
2 parents 37cfd70 + 28d0762 commit a9e87d9

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16 files changed

+466
-52
lines changed

16 files changed

+466
-52
lines changed

‎jasper_library/hdl_sources/axi4_lite/axi4lite_pkg.vhd‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -133,4 +133,4 @@ package axi4lite_pkg is
133133
((OTHERS => '0'), (OTHERS => '0'), (OTHERS => '0'), '0', '0');
134134
CONSTANT c_axi4stream_siso_rst : t_axi4stream_siso :=
135135
(tready => '0');
136-
end axi4lite_pkg;
136+
end axi4lite_pkg;

‎jasper_library/hdl_sources/forty_gbe/cont_microblaze/EMB123701U1R1-v3.20.58-0-g8c875c6-master.elf‎

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‎jasper_library/hdl_sources/forty_gbe/cont_microblaze/EMB123701U1R1.elf‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
EMB123701U1R1-v3.20.36-0-g00f7671-master.elf
1+
EMB123701U1R1-v3.20.58-0-g8c875c6-master.elf

‎jasper_library/hdl_sources/sys_block/counter.v‎

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
//============================================================================//
2+
// //
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// Parameterize Counter //
4+
// //
5+
// Module name: counter //
6+
// Desc: parameterized counter, counts up/down in any increment //
7+
// Date: Oct 2011 //
8+
// Developer: Rurik Primiani & Wesley New //
9+
// Adapted by: Mathews Chirindo //
10+
// Date: Jan 2020 //
11+
// Licence: GNU General Public License ver 3 //
12+
// Notes: //
13+
// //
14+
//============================================================================//
15+
16+
module counter #(
17+
//==============================
18+
// Top level block parameters
19+
//==============================
20+
parameter DATA_WIDTH = 32, // number of bits in counters
21+
parameter COUNT_FROM = 0, // start with this number
22+
parameter COUNT_TO = 2**(DATA_WIDTH), // value to count to in CL case
23+
parameter STEP = 1 // negative or positive, sets direction
24+
) (
25+
//===============
26+
// Input Ports
27+
//===============
28+
input user_clk,
29+
input en,
30+
input user_rst,
31+
32+
//===============
33+
// Output Ports
34+
//===============
35+
output reg [DATA_WIDTH-1:0] count_out,
36+
output we
37+
);
38+
39+
assign we = 1'b1;
40+
41+
// Synchronous logic
42+
always @(posedge user_clk) begin
43+
// if ACTIVE_LOW_RST is defined then reset on a low
44+
// this should be defined on a system-wide basis
45+
if (`ifdef ACTIVE_LOW_RST user_rst `else !user_rst `endif) begin
46+
if (en == 1) begin
47+
count_out <= count_out + STEP;
48+
end
49+
end
50+
else begin
51+
count_out <= COUNT_FROM;
52+
end // else: if(rst != 0)
53+
end
54+
endmodule
55+

‎jasper_library/memory.py‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
class Register(object):
2-
def __init__(self, name, nbytes=4, offset=0, mode='r', default_val=0, ram=False, ram_size=-1):
2+
def __init__(self, name, nbytes=4, offset=0, mode='r',
3+
default_val=0, ram=False, ram_size=-1, data_width=32):
34
"""
45
A class to encapsulate a register's parameters. This is used when
56
instantiating a device with a large address space, but it is desirable
@@ -48,3 +49,8 @@ def modify_top(self,top):
4849
self.ram = ram
4950
#self.ram_size = ram_size
5051
self.default_val = default_val
52+
53+
# Addded to make provision for variable-size BRAMs in AXI4-Lite devices
54+
# - Placing here for now because toolflow.py:generate_xml_memory_map
55+
# has access to the memory.Register object in the XML generation
56+
self.data_width = data_width

‎jasper_library/platforms/red_pitaya_10.yaml‎

Lines changed: 123 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,129 @@ pins:
120120
DAC_IQRESET:
121121
iostd: LVCMOS33
122122
loc: N15
123-
123+
FIXED_IO_ddr_vrp:
124+
iostd: SSTL15_T_DCI
125+
loc: H5
126+
FIXED_IO_ddr_vrn:
127+
iostd: SSTL15_T_DCI
128+
loc: G5
129+
DDR_we_n:
130+
iostd: SSTL15
131+
loc: M5
132+
DDR_RAS_n:
133+
iostd: SSTL15
134+
loc: P4
135+
DDR_ODT:
136+
iostd: SSTL15
137+
loc: N5
138+
DDR_reset_n:
139+
iostd: SSTL15
140+
loc: B4
141+
DDR_DQS_p:
142+
iostd: DIFF_SSTL15_T_DCI
143+
loc:
144+
- C2
145+
- G2
146+
- R2
147+
- W5
148+
DDR_DQS_n:
149+
iostd: DIFF_SSTL15_T_DCI
150+
loc:
151+
- B2
152+
- F2
153+
- T2
154+
- W4
155+
DDR_DQ:
156+
iostd: SSTL15_T_DCI
157+
loc:
158+
- C3
159+
- B3
160+
- A2
161+
- A4
162+
- D3
163+
- D1
164+
- C1
165+
- E1
166+
- E2
167+
- E3
168+
- G3
169+
- H3
170+
- J3
171+
- H2
172+
- H1
173+
- J1
174+
- P1
175+
- P3
176+
- R3
177+
- R1
178+
- T4
179+
- U4
180+
- U2
181+
- U3
182+
- V1
183+
- Y3
184+
- W1
185+
- Y4
186+
- Y2
187+
- W3
188+
- V2
189+
- V3
190+
DDR_DM:
191+
iostd: DIFF_SSTL15_T_DCI
192+
loc:
193+
- A1
194+
- F1
195+
- T1
196+
- Y1
197+
DDR_CS_n:
198+
iostd: SSTL15
199+
loc: N1
200+
DDR_CKE:
201+
iostd: SSTL15
202+
loc: N3
203+
DDR_Ck_p:
204+
iostd: SSTL15
205+
loc: L2
206+
DDR_Ck_n:
207+
iostd: SSTL15
208+
loc: M2
209+
DDR_CAS_n:
210+
iostd: SSTL15
211+
loc: P5
212+
DDR_ba:
213+
iostd: DIFF_SSTL15
214+
loc:
215+
- L5
216+
- R4
217+
- J5
218+
DDR_Addr:
219+
iostd: SSTL15
220+
loc:
221+
- N2
222+
- K2
223+
- M3
224+
- K3
225+
- M4
226+
- L1
227+
- L4
228+
- K4
229+
- K1
230+
- J4
231+
- F5
232+
- G4
233+
- E4
234+
- D4
235+
- F4
236+
FIXED_IO_ps_porb:
237+
iostd: LVCMOS33
238+
loc: C7
239+
FIXED_IO_ps_srstb:
240+
iostd: LVCMOS33
241+
loc: B10
242+
FIXED_IO_ps_clk:
243+
iostd: LVCMOS33
244+
loc: E7
245+
124246

125247

126248

‎jasper_library/platforms/red_pitaya_14.yaml‎

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,137 @@ pins:
138138
DAC_IQRESET:
139139
iostd: LVCMOS33
140140
loc: N15
141+
FIXED_IO_ddr_vrp:
142+
iostd: SSTL15_T_DCI
143+
loc: H5
144+
FIXED_IO_ddr_vrn:
145+
iostd: SSTL15_T_DCI
146+
loc: G5
147+
DDR_we_n:
148+
iostd: SSTL15
149+
loc: M5
150+
DDR_RAS_n:
151+
iostd: SSTL15
152+
loc: P4
153+
DDR_ODT:
154+
iostd: SSTL15
155+
loc: N5
156+
DDR_reset_n:
157+
iostd: SSTL15
158+
loc: B4
159+
DDR_DQS_p:
160+
iostd: DIFF_SSTL15_T_DCI
161+
loc:
162+
- C2
163+
- G2
164+
- R2
165+
- W5
166+
DDR_DQS_n:
167+
iostd: DIFF_SSTL15_T_DCI
168+
loc:
169+
- B2
170+
- F2
171+
- T2
172+
- W4
173+
DDR_DQ:
174+
iostd: SSTL15_T_DCI
175+
loc:
176+
- C3
177+
- B3
178+
- A2
179+
- A4
180+
- D3
181+
- D1
182+
- C1
183+
- E1
184+
- E2
185+
- E3
186+
- G3
187+
- H3
188+
- J3
189+
- H2
190+
- H1
191+
- J1
192+
- P1
193+
- P3
194+
- R3
195+
- R1
196+
- T4
197+
- U4
198+
- U2
199+
- U3
200+
- V1
201+
- Y3
202+
- W1
203+
- Y4
204+
- Y2
205+
- W3
206+
- V2
207+
- V3
208+
DDR_DM:
209+
iostd: DIFF_SSTL15_T_DCI
210+
loc:
211+
- A1
212+
- F1
213+
- T1
214+
- Y1
215+
DDR_CS_n:
216+
iostd: SSTL15
217+
loc: N1
218+
DDR_CKE:
219+
iostd: SSTL15
220+
loc: N3
221+
DDR_Ck_p:
222+
iostd: SSTL15
223+
loc: L2
224+
DDR_Ck_n:
225+
iostd: SSTL15
226+
loc: M2
227+
DDR_CAS_n:
228+
iostd: SSTL15
229+
loc: P5
230+
DDR_ba:
231+
iostd: DIFF_SSTL15
232+
loc:
233+
- L5
234+
- R4
235+
- J5
236+
DDR_Addr:
237+
iostd: SSTL15
238+
loc:
239+
- N2
240+
- K2
241+
- M3
242+
- K3
243+
- M4
244+
- L1
245+
- L4
246+
- K4
247+
- K1
248+
- J4
249+
- F5
250+
- G4
251+
- E4
252+
- D4
253+
- F4
254+
FIXED_IO_ps_porb:
255+
iostd: LVCMOS33
256+
loc: C7
257+
FIXED_IO_ps_srstb:
258+
iostd: LVCMOS33
259+
loc: B10
260+
FIXED_IO_ps_clk:
261+
iostd: LVCMOS33
262+
loc: E7
263+
264+
265+
266+
267+
268+
269+
270+
271+
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