Planar ortho pr

cli/cmd/physical_design/cmd_physical_design.hpp

@@ -18,6 +18,7 @@
 #endif
 #include "include/optimize.hpp"
 #include "include/ortho.hpp"
+#include "include/plane.hpp"
 // NOLINTEND(misc-include-cleaner)
 
 namespace alice
@@ -36,6 +37,7 @@ ALICE_ADD_COMMAND(onepass, FICTION_CLI_CATEGORY_PHYSICAL_DESIGN)
 #endif
 ALICE_ADD_COMMAND(optimize, FICTION_CLI_CATEGORY_PHYSICAL_DESIGN)
 ALICE_ADD_COMMAND(ortho, FICTION_CLI_CATEGORY_PHYSICAL_DESIGN)
+ALICE_ADD_COMMAND(plane, FICTION_CLI_CATEGORY_PHYSICAL_DESIGN)
 
 }  // namespace alice
 

cli/cmd/physical_design/include/plane.hpp

@@ -0,0 +1,82 @@
+//
+// Created by benjamin on 21.11.25.
+//
+
+#ifndef FICTION_CMD_PLANE_HPP
+#define FICTION_CMD_PLANE_HPP
+
+#include <fiction/algorithms/network_transformation/fanout_substitution.hpp>
+#include <fiction/algorithms/network_transformation/network_balancing.hpp>
+#include <fiction/algorithms/network_transformation/node_duplication_planarization.hpp>
+#include <fiction/algorithms/physical_design/planar_layout_from_network_embedding.hpp>
+
+#include <alice/alice.hpp>
+#include <nlohmann/json.hpp>
+
+#include <cstdint>
+
+namespace alice
+{
+/**
+ * Executes the physical design approach Planar Layout from Network Embedding (PLANE), which finds a valid placement and
+ * routing without crossings given a planar network embedding.
+ *
+ * See include/fiction/algorithms/physical_design/planar_layout_from_network_embedding.hpp for more details.
+ */
+class plane_command final : public command
+{
+  public:
+    /**
+     * Standard constructor. Adds descriptive information, options, and flags.
+     *
+     * @param e alice::environment that specifies stores etc.
+     */
+    explicit plane_command(const environment::ptr& e);
+
+  protected:
+    /**
+     * Function to perform the physical design call. Generates a placed and routed FCN gate layout.
+     */
+    void execute() override;
+
+    /**
+     * Logs the resulting information in a log file.
+     *
+     * @return JSON object containing information about the physical design process.
+     */
+    nlohmann::json log() const override;
+
+  private:
+    /**
+     * Parameters for fanout substitution.
+     */
+    fiction::fanout_substitution_params fan_ps{};
+    /**
+     * Parameters for network path balancing.
+     */
+    fiction::network_balancing_params bal_ps{};
+    /**
+     * Parameters for planarization via node duplication.
+     */
+    fiction::node_duplication_planarization_params dup_ps{};
+    /**
+     * Parameters for planar layout generation from the network embedding.
+     */
+    fiction::planar_layout_from_network_embedding_params ps{};
+    /**
+     * Statistics collected during planar layout generation.
+     */
+    fiction::planar_layout_from_network_embedding_stats st{};
+    /**
+     * Number of clock phases used in the layout.
+     */
+    uint8_t num_clock_phases = 4u;
+    /**
+     * Determines whether primary output order is kept (0) or randomized (1).
+     */
+    uint32_t po_order{0u};
+};
+
+}  // namespace alice
+
+#endif  // FICTION_CMD_PLANE_HPP

cli/cmd/physical_design/src/plane.cpp

@@ -0,0 +1,133 @@
+//
+// Created by benjamin on 21.11.25.
+//
+
+#include "cmd/physical_design/include/plane.hpp"
+
+#include "stores.hpp"  // NOLINT(misc-include-cleaner)
+
+#include <fiction/algorithms/network_transformation/fanout_substitution.hpp>
+#include <fiction/algorithms/network_transformation/network_balancing.hpp>
+#include <fiction/algorithms/network_transformation/node_duplication_planarization.hpp>
+#include <fiction/algorithms/physical_design/planar_layout_from_network_embedding.hpp>
+#include <fiction/layouts/clocking_scheme.hpp>
+#include <fiction/networks/views/mutable_rank_view.hpp>
+#include <fiction/types.hpp>
+#include <fiction/utils/network_utils.hpp>
+
+#include <alice/alice.hpp>
+#include <fmt/format.h>
+#include <mockturtle/utils/stopwatch.hpp>
+#include <nlohmann/json.hpp>
+
+#include <exception>
+#include <memory>
+#include <stdexcept>
+#include <string>
+#include <variant>
+
+namespace alice
+{
+
+plane_command::plane_command(const environment::ptr& e) :
+        command(e, "First, a planar embedding is obtained by performing fanout substitution, path balancing, and "
+                   "planarization (node duplication). Then, scalable placement and routing are carried out on the "
+                   "planar layout of the current logic network in store. Compared to the gold algorithm, the "
+                   "resulting layout may occupy more area, but it is generated in reasonable runtime.")
+{
+    // fanout substitution options
+    fan_ps.degree = 2;
+    // balancing option
+    bal_ps.unify_outputs = true;
+    // planarization option
+    add_option("--po-order, -p", po_order, "PO order: keep=0, random=1")->set_type_name("{0,1}");
+    // plane options
+    add_option("--clock_numbers,-n", num_clock_phases, "Number of clock phases to be used {3 or 4}");
+    add_flag("--verbose,-v", ps.verbose, "Be verbose");
+}
+
+void plane_command::execute()
+{
+    auto& lns = store<fiction::logic_network_t>();
+    auto& gls = store<fiction::gate_layout_t>();
+
+    if (lns.empty())
+    {
+        env->out() << "[w] no logic network in store\n";
+        return;
+    }
+    // error case: phases out of range
+    if (num_clock_phases != 3u && num_clock_phases != 4u)
+    {
+        env->out() << "[e] only 3- and 4-phase clocking schemes are supported\n";
+        ps = {};
+        return;
+    }
+
+    ps.number_of_clock_phases = num_clock_phases == 3 ? fiction::num_clks::THREE : fiction::num_clks::FOUR;
+
+    switch (po_order)
+    {
+        case 0u:
+        {
+            dup_ps.po_order = fiction::node_duplication_planarization_params::output_order::KEEP_PO_ORDER;
+            break;
+        }
+        case 1u:
+        {
+            dup_ps.po_order = fiction::node_duplication_planarization_params::output_order::RANDOM_PO_ORDER;
+            break;
+        }
+        default:
+        {
+            env->out() << "[w] invalid --po-order, defaulting to keep\n";
+            dup_ps.po_order = fiction::node_duplication_planarization_params::output_order::KEEP_PO_ORDER;
+            break;
+        }
+    }
+
+    const auto perform_fanouts_and_balance = [this](auto&& ntk_ptr)
+    {
+        auto tec_f = fiction::fanout_substitution<fiction::tec_nt>(*ntk_ptr, fan_ps);
+        return std::make_shared<fiction::tec_nt>(fiction::network_balancing<fiction::tec_nt>(tec_f, bal_ps));
+    };
+
+    auto tec_b = std::visit(perform_fanouts_and_balance, lns.current());
+
+    const fiction::mutable_rank_view vpi_r(*tec_b);
+
+    auto planarized_ntk = fiction::node_duplication_planarization(vpi_r, dup_ps);
+
+    try
+    {
+        gls.extend() = std::make_shared<fiction::cart_gate_clk_lyt>(
+            fiction::plane<fiction::cart_gate_clk_lyt>(planarized_ntk, ps, &st));
+    }
+    catch (const fiction::high_degree_fanin_exception& e)
+    {
+        env->out() << fmt::format("[e] {}\n", e.what());
+    }
+    catch (const std::invalid_argument& e)
+    {
+        env->out() << fmt::format("[e] {}\n", e.what());
+    }
+    catch (const std::exception& e)
+    {
+        env->out() << fmt::format("[e] unexpected error: {}\n", e.what());
+    }
+
+    fan_ps = {};
+    bal_ps = {};
+    dup_ps = {};
+}
+
+nlohmann::json plane_command::log() const
+{
+    return nlohmann::json{{"runtime in seconds", mockturtle::to_seconds(st.time_total)},
+                          {"number of gates", st.num_gates},
+                          {"number of wires", st.num_wires},
+                          {"number of crossings", st.num_crossings},
+                          {"layout", {{"x-size", st.x_size}, {"y-size", st.y_size}, {"area", st.x_size * st.y_size}}}};
+}
+
+}  // namespace alice

docs/changelog.rst

@@ -10,6 +10,9 @@ Unreleased
 
 Added
 #####
+- Algorithms:
+    - Node Duplication Planarization, reimplemented from "Fabricatable Interconnect and Molecular QCA Circuits" by Amitabh Chaudhary, Danny Ziyi Chen, Xiaobo Sharon Hu, Michael T. Niemier, Ramprasad Ravichandran, and Kevin Whitton.
+    - Planar Layout from Network Embedding (PLANE) for generating planar 2DDWave-clocked Cartesian gate-level layouts in a fast and scalable fashion.
 - Documentation:
     - Added ``AGENTS.md`` to guide AI agents in the repository