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alaindargelasalaindargelas
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gen if-else
1 parent 8a2cc9b commit 250e669

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34 files changed

+775
-288
lines changed

34 files changed

+775
-288
lines changed

‎src/DesignCompile/CompileGenStmt.cpp‎

Lines changed: 40 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -79,22 +79,53 @@ void CompileHelper::compileGenStmt(ModuleDefinition* component,
7979
if (fC->Type(stmtId) == VObjectType::slIf_generate_construct) {
8080
NodeId ifElseId = fC->Child(stmtId);
8181
if (fC->Type(ifElseId) == VObjectType::slIF) {
82+
// lookahead
83+
NodeId tmp = ifElseId;
84+
bool ifelse = false;
85+
while (tmp) {
86+
if (fC->Type(tmp) == VObjectType::slElse) {
87+
ifelse = true;
88+
break;
89+
}
90+
tmp = fC->Sibling(tmp);
91+
}
92+
8293
NodeId condId = fC->Sibling(ifElseId);
8394
expr* cond = (expr*)compileExpression(component, fC, condId,
8495
compileDesign, Reduce::No, nullptr);
8596
NodeId stmtId = fC->Sibling(condId);
86-
gen_if* genif = s.MakeGen_if();
87-
genif->VpiCondition(cond);
88-
fC->populateCoreMembers(ifElseId, ifElseId, genif);
89-
begin* stmt = s.MakeBegin();
90-
VectorOfany* stmts = compileStmt(component, fC, stmtId, compileDesign,
91-
Reduce::No, nullptr, nullptr, true);
92-
stmt->Stmts(stmts);
93-
genif->VpiStmt(stmt);
97+
gen_stmt* genstmt = nullptr;
98+
if (ifelse) {
99+
gen_if_else* genif = s.MakeGen_if_else();
100+
genstmt = genif;
101+
genif->VpiCondition(cond);
102+
begin* stmt = s.MakeBegin();
103+
VectorOfany* stmts = compileStmt(component, fC, stmtId, compileDesign,
104+
Reduce::No, nullptr, nullptr, true);
105+
stmt->Stmts(stmts);
106+
genif->VpiStmt(stmt);
107+
NodeId ElseId = fC->Sibling(stmtId);
108+
NodeId elseStmtId = fC->Sibling(ElseId);
109+
stmts = compileStmt(component, fC, elseStmtId, compileDesign,
110+
Reduce::No, nullptr, nullptr, true);
111+
stmt = s.MakeBegin();
112+
stmt->Stmts(stmts);
113+
genif->VpiElseStmt(stmt);
114+
} else {
115+
gen_if* genif = s.MakeGen_if();
116+
genstmt = genif;
117+
genif->VpiCondition(cond);
118+
fC->populateCoreMembers(ifElseId, ifElseId, genif);
119+
begin* stmt = s.MakeBegin();
120+
VectorOfany* stmts = compileStmt(component, fC, stmtId, compileDesign,
121+
Reduce::No, nullptr, nullptr, true);
122+
stmt->Stmts(stmts);
123+
genif->VpiStmt(stmt);
124+
}
94125
if (component->getGenStmts() == nullptr) {
95126
component->setGenStmts(s.MakeGen_stmtVec());
96127
}
97-
component->getGenStmts()->push_back(genif);
128+
component->getGenStmts()->push_back(genstmt);
98129
}
99130
}
100131
}

‎tests/Bindings/Bindings.log‎

Lines changed: 53 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1352,20 +1352,21 @@ AST_DEBUG_END
13521352
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
13531353
always 2
13541354
assignment 3
1355-
begin 4
1355+
begin 5
13561356
bit_select 3
13571357
class_defn 8
13581358
class_typespec 4
13591359
class_var 3
1360-
constant 165
1361-
cont_assign 6
1360+
constant 166
1361+
cont_assign 7
13621362
design 1
13631363
enum_const 23
13641364
enum_typespec 10
13651365
enum_var 1
13661366
event_control 1
13671367
function 9
1368-
gen_if 2
1368+
gen_if 1
1369+
gen_if_else 1
13691370
gen_scope 2
13701371
gen_scope_array 2
13711372
if_else 1
@@ -1377,14 +1378,14 @@ logic_net 21
13771378
logic_typespec 18
13781379
logic_var 2
13791380
module_inst 26
1380-
operation 53
1381+
operation 55
13811382
package 5
13821383
param_assign 35
13831384
parameter 35
13841385
port 4
13851386
range 22
13861387
ref_module 2
1387-
ref_obj 55
1388+
ref_obj 58
13881389
string_typespec 3
13891390
sys_func_call 3
13901391
task 9
@@ -1399,20 +1400,21 @@ unsupported_typespec 1
13991400
=== UHDM Object Stats Begin (Elaborated Model) ===
14001401
always 5
14011402
assignment 8
1402-
begin 7
1403+
begin 8
14031404
bit_select 5
14041405
class_defn 8
14051406
class_typespec 4
14061407
class_var 3
1407-
constant 176
1408-
cont_assign 10
1408+
constant 177
1409+
cont_assign 11
14091410
design 1
14101411
enum_const 28
14111412
enum_typespec 11
14121413
enum_var 1
14131414
event_control 3
14141415
function 18
1415-
gen_if 2
1416+
gen_if 1
1417+
gen_if_else 1
14161418
gen_scope 3
14171419
gen_scope_array 3
14181420
if_else 3
@@ -1424,14 +1426,14 @@ logic_net 21
14241426
logic_typespec 18
14251427
logic_var 2
14261428
module_inst 26
1427-
operation 73
1429+
operation 75
14281430
package 5
14291431
param_assign 35
14301432
parameter 35
14311433
port 6
14321434
range 22
14331435
ref_module 2
1434-
ref_obj 85
1436+
ref_obj 88
14351437
string_typespec 3
14361438
sys_func_call 3
14371439
task 18
@@ -2587,7 +2589,7 @@ design: (work@dut1)
25872589
|UINT:0
25882590
|vpiConstType:9
25892591
|vpiGenStmt:
2590-
\_gen_if: , line:41:6, endln:41:8
2592+
\_gen_if_else:
25912593
|vpiParent:
25922594
\_module_inst: work@dut2 (work@dut2), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:35:1, endln:50:10
25932595
|vpiCondition:
@@ -2608,6 +2610,44 @@ design: (work@dut1)
26082610
|vpiConstType:9
26092611
|vpiStmt:
26102612
\_begin:
2613+
|vpiElseStmt:
2614+
\_begin:
2615+
|vpiStmt:
2616+
\_cont_assign: , line:47:15, endln:47:44
2617+
|vpiRhs:
2618+
\_operation: , line:47:19, endln:47:44
2619+
|vpiParent:
2620+
\_cont_assign: , line:47:15, endln:47:44
2621+
|vpiTypespec:
2622+
\_string_typespec:
2623+
|vpiOpType:67
2624+
|vpiOperand:
2625+
\_operation: , line:47:34, endln:47:43
2626+
|vpiParent:
2627+
\_operation: , line:47:19, endln:47:44
2628+
|vpiOpType:22
2629+
|vpiOperand:
2630+
\_constant: , line:47:34, endln:47:38
2631+
|vpiParent:
2632+
\_operation: , line:47:34, endln:47:43
2633+
|vpiDecompile:1'b1
2634+
|vpiSize:1
2635+
|BIN:1
2636+
|vpiConstType:3
2637+
|vpiOperand:
2638+
\_ref_obj: (i), line:47:42, endln:47:43
2639+
|vpiParent:
2640+
\_operation: , line:47:34, endln:47:43
2641+
|vpiName:i
2642+
|vpiActual:
2643+
\_logic_net: ([email protected]), line:37:36, endln:37:37
2644+
|vpiLhs:
2645+
\_ref_obj: (o), line:47:15, endln:47:16
2646+
|vpiParent:
2647+
\_cont_assign: , line:47:15, endln:47:44
2648+
|vpiName:o
2649+
|vpiActual:
2650+
\_logic_net: ([email protected]), line:38:36, endln:38:37
26112651
|uhdmallModules:
26122652
\_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10
26132653
|vpiParent:

‎tests/ConcatOrder/ConcatOrder.log‎

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -358,14 +358,14 @@ AST_DEBUG_END
358358
[INF:UH0706] Creating UHDM Model...
359359

360360
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
361-
begin 1
361+
begin 2
362362
bit_select 5
363363
bit_typespec 4
364364
constant 116
365365
design 1
366366
enum_const 8
367367
enum_typespec 4
368-
gen_if 1
368+
gen_if_else 1
369369
gen_scope 2
370370
gen_scope_array 2
371371
hier_path 2
@@ -379,7 +379,7 @@ packed_array_typespec 8
379379
param_assign 42
380380
parameter 50
381381
range 12
382-
ref_module 2
382+
ref_module 3
383383
ref_obj 50
384384
string_typespec 24
385385
struct_typespec 34
@@ -390,14 +390,14 @@ typespec_member 34
390390
[INF:UH0707] Elaborating UHDM...
391391

392392
=== UHDM Object Stats Begin (Elaborated Model) ===
393-
begin 1
393+
begin 2
394394
bit_select 5
395395
bit_typespec 4
396396
constant 123
397397
design 1
398398
enum_const 8
399399
enum_typespec 4
400-
gen_if 1
400+
gen_if_else 1
401401
gen_scope 3
402402
gen_scope_array 3
403403
hier_path 2
@@ -411,7 +411,7 @@ packed_array_typespec 8
411411
param_assign 42
412412
parameter 50
413413
range 12
414-
ref_module 2
414+
ref_module 3
415415
ref_obj 50
416416
string_typespec 24
417417
struct_typespec 34
@@ -1560,7 +1560,7 @@ design: (work@testbench)
15601560
\_import_typespec: (bp_common_pkg), line:40:9, endln:40:25
15611561
|vpiDefName:work@testbench
15621562
|vpiGenStmt:
1563-
\_gen_if: , line:48:2, endln:48:4
1563+
\_gen_if_else:
15641564
|vpiParent:
15651565
\_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11
15661566
|vpiCondition:
@@ -1585,6 +1585,12 @@ design: (work@testbench)
15851585
\_ref_module: work@GOOD (good), line:49:11, endln:49:15
15861586
|vpiName:good
15871587
|vpiDefName:work@GOOD
1588+
|vpiElseStmt:
1589+
\_begin:
1590+
|vpiStmt:
1591+
\_ref_module: work@BAD (bad), line:51:10, endln:51:13
1592+
|vpiName:bad
1593+
|vpiDefName:work@BAD
15881594
|uhdmtopModules:
15891595
\_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/ConcatOrder/dut.sv, line:39:2, endln:54:11
15901596
|vpiName:work@testbench

‎tests/ElabCParam/ElabCParam.log‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -882,7 +882,7 @@ AST_DEBUG_END
882882
[INF:UH0706] Creating UHDM Model...
883883

884884
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
885-
begin 1
885+
begin 2
886886
bit_typespec 12
887887
class_defn 8
888888
class_typespec 4
@@ -894,7 +894,7 @@ enum_const 5
894894
enum_typespec 1
895895
enum_var 1
896896
function 9
897-
gen_if 1
897+
gen_if_else 1
898898
gen_scope 16
899899
gen_scope_array 16
900900
indexed_part_select 8
@@ -917,7 +917,7 @@ task 9
917917
[INF:UH0707] Elaborating UHDM...
918918

919919
=== UHDM Object Stats Begin (Elaborated Model) ===
920-
begin 1
920+
begin 2
921921
bit_typespec 12
922922
class_defn 8
923923
class_typespec 4
@@ -929,7 +929,7 @@ enum_const 10
929929
enum_typespec 2
930930
enum_var 1
931931
function 18
932-
gen_if 1
932+
gen_if_else 1
933933
gen_scope 32
934934
gen_scope_array 32
935935
indexed_part_select 8
@@ -1675,7 +1675,7 @@ design: (work@socket_1n)
16751675
\_parameter: (work@prim_fifo_sync.Depth), line:3:26, endln:3:31
16761676
|vpiDefName:work@prim_fifo_sync
16771677
|vpiGenStmt:
1678-
\_gen_if: , line:8:3, endln:8:5
1678+
\_gen_if_else:
16791679
|vpiParent:
16801680
\_module_inst: work@prim_fifo_sync (work@prim_fifo_sync), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:2:1, endln:21:10
16811681
|vpiCondition:
@@ -1713,6 +1713,8 @@ design: (work@socket_1n)
17131713
|vpiName:depth
17141714
|vpiActual:
17151715
\_logic_net: (depth)
1716+
|vpiElseStmt:
1717+
\_begin:
17161718
|uhdmallModules:
17171719
\_module_inst: work@socket_1n (work@socket_1n), file:${SURELOG_DIR}/tests/ElabCParam/dut.sv, line:38:1, endln:51:10
17181720
|vpiParent:

‎tests/ForElab/ForElab.log‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -75,14 +75,14 @@ Instance tree:
7575
[INF:UH0706] Creating UHDM Model...
7676

7777
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
78-
begin 2
78+
begin 4
7979
bit_select 1
8080
bit_typespec 2
8181
constant 140
8282
cont_assign 1
8383
design 1
8484
gate 6
85-
gen_if 2
85+
gen_if_else 2
8686
gen_scope 10
8787
gen_scope_array 10
8888
int_typespec 21
@@ -292,7 +292,7 @@ design: (work@tlul_socket_m1)
292292
|vpiTypedef:
293293
\_logic_typespec: , line:22:9, endln:22:9
294294
|vpiGenStmt:
295-
\_gen_if: , line:28:3, endln:28:5
295+
\_gen_if_else:
296296
|vpiParent:
297297
\_module_inst: work@prim_arbiter_tree (work@prim_arbiter_tree), file:${SURELOG_DIR}/tests/ForElab/top.v, line:16:1, endln:47:10
298298
|vpiCondition:
@@ -338,14 +338,16 @@ design: (work@tlul_socket_m1)
338338
|vpiName:valid_o
339339
|vpiActual:
340340
\_logic_net: (valid_o)
341+
|vpiElseStmt:
342+
\_begin:
341343
|uhdmallModules:
342344
\_module_inst: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10
343345
|vpiParent:
344346
\_design: (work@tlul_socket_m1)
345347
|vpiFullName:work@tlul_socket_m1
346348
|vpiDefName:work@tlul_socket_m1
347349
|vpiGenStmt:
348-
\_gen_if: , line:52:3, endln:52:5
350+
\_gen_if_else:
349351
|vpiParent:
350352
\_module_inst: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10
351353
|vpiCondition:
@@ -373,6 +375,8 @@ design: (work@tlul_socket_m1)
373375
|vpiConstType:6
374376
|vpiStmt:
375377
\_begin:
378+
|vpiElseStmt:
379+
\_begin:
376380
|uhdmtopModules:
377381
\_module_inst: work@tlul_socket_m1 (work@tlul_socket_m1), file:${SURELOG_DIR}/tests/ForElab/top.v, line:49:1, endln:68:10
378382
|vpiName:work@tlul_socket_m1

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