[ChiselSim] Add preprocessor defs to LayerControl

Add a member function `preprocessorDefines` to `LayerControl.Type` which
will return any preprocessor defines that should be set to enable the
requested layers.

Add an abstract member function, `getLayerSubset`, which layer control
concrete types implement to make the preprocessor define function work.

Signed-off-by: Schuyler Eldridge <[email protected]>

Author: seldridge

src/main/scala-2/chisel3/simulator/LayerControl.scala

@@ -1,7 +1,11 @@
 package chisel3.simulator
 
 import java.io.File
-import chisel3.layer.Layer
+import chisel3.RawModule
+import chisel3.layer.{ABI, Layer}
+import chisel3.simulator.ElaboratedModule
+import chisel3.stage.DesignAnnotation
+import svsim.CommonCompilationSettings.VerilogPreprocessorDefine
 
 /** Utilities for enabling and disabling Chisel layers */
 object LayerControl {
@@ -22,11 +26,41 @@ object LayerControl {
       * @param layerFilename the filename of a layer
       */
     protected def shouldEnable(layerFilename: String): Boolean
+
+    /** Return the layers that should be enabled in a circuit.  The layers must exist in the design.
+      *
+      * @param design an Annotation that contains an elaborated design used to check that the requested layers exist
+      * @return all layers that should be enabled
+      * @throws IllegalArgumentException if the requested layers
+      */
+    protected def getLayerSubset(module: ElaboratedModule[_]): Seq[Layer]
+
+    /** Return the preprocessor defines that should be set to enable the layers of
+      * this `LayerControl.Type`.
+      *
+      * This requires passing an elaborated module in order to know what layers
+      * exist in the design.
+      *
+      * @param module an elaborated module
+      * @return preprocessor defines to control the enabling of these layers
+      */
+    final def preprocessorDefines(
+      module: ElaboratedModule[_ <: RawModule]
+    ): Seq[VerilogPreprocessorDefine] = getLayerSubset(module).flatMap {
+      case layer =>
+        layer.config.abi match {
+          case abi: chisel3.layer.ABI.PreprocessorDefine.type =>
+            Some(VerilogPreprocessorDefine(abi.toMacroIdentifier(layer, module.wrapped.circuitName)))
+          case _ => None
+        }
+    }
   }
 
   /** Enable all layers */
   final case object EnableAll extends Type {
     override protected def shouldEnable(layerFilename: String) = true
+
+    override protected def getLayerSubset(module: ElaboratedModule[_]): Seq[Layer] = module.layers
   }
 
   /** Enable only the specified layers
@@ -46,6 +80,19 @@ object LayerControl {
       }
     }
     override protected def shouldEnable(filename: String) = _shouldEnable(filename)
+
+    override protected def getLayerSubset(module: ElaboratedModule[_]): Seq[Layer] = {
+      val definedLayers = module.layers
+      layers.foreach { layer =>
+        require(
+          definedLayers.contains(layer),
+          s"""cannot enable layer '${layer.fullName}' as it is not one of the defined layers: ${definedLayers.map(
+            _.fullName
+          )}"""
+        )
+      }
+      layers
+    }
   }
 
   /** Disables all layers.  This is the same as `Enable()`. */

src/main/scala-2/chisel3/simulator/package.scala

@@ -3,6 +3,7 @@ package chisel3
 import svsim._
 import chisel3.reflect.DataMirror
 import chisel3.experimental.dataview.reifyIdentityView
+import chisel3.stage.DesignAnnotation
 import scala.collection.mutable
 import java.nio.file.{Files, Path, Paths}
 import firrtl.seqToAnnoSeq
@@ -14,7 +15,8 @@ package object simulator {
     */
   final class ElaboratedModule[T] private[simulator] (
     private[simulator] val wrapped: T,
-    private[simulator] val ports:   Seq[(Data, ModuleInfo.Port)])
+    private[simulator] val ports:   Seq[(Data, ModuleInfo.Port)],
+    private[simulator] val layers:  Seq[chisel3.layer.Layer])
 
   /**
     * A class that enables using a Chisel module to control an `svsim.Simulation`.
@@ -222,7 +224,8 @@ package object simulator {
           ports = ports.map(_._2)
         )
       )
-      new ElaboratedModule(dut, ports)
+      val layers = outputAnnotations.collectFirst { case DesignAnnotation(_, layers) => layers }.get
+      new ElaboratedModule(dut, ports, layers)
     }
   }
 }