[ChiselSim] Add inline layer control

Extend ChiselSim with the ability to control inline layers.  This requires
untangling some of the way that compilation settings are passed into a
`Simulator` because these options need to be added to after Chisel
elaboration.  E.g., to enable all inline layers, this requires knowing all
the layers that were created.  This didn't come up previously with extract
layers as all layer files could be blindly included for this case.

In susbequent commits, I will cleanup the way that extract layers work to
use the same code that is introduced here.

Signed-off-by: Schuyler Eldridge <[email protected]>

Author: seldridge

src/main/scala-2/chisel3/simulator/EphemeralSimulator.scala

@@ -23,7 +23,7 @@ object EphemeralSimulator extends PeekPokeAPI {
     layerControl: LayerControl.Type = LayerControl.EnableAll
   )(body:         (T) => Unit
   ): Unit = {
-    makeSimulator(layerControl).simulate(module)({ module => body(module.wrapped) }).result
+    makeSimulator(layerControl).simulate(module, layerControl)({ module => body(module.wrapped) }).result
   }
 
   private class DefaultSimulator(val workspacePath: String, layerControl: LayerControl.Type)

src/main/scala-2/chisel3/simulator/Simulator.scala

@@ -99,11 +99,16 @@ trait Simulator {
   def customSimulationWorkingDirectory: Option[String] = None
   def verbose:                          Boolean = false
   def firtoolArgs:                      Seq[String] = Seq()
+  def commonCompilationSettings: CommonCompilationSettings
 
-  private[simulator] def processBackends(processor: Simulator.BackendProcessor): Unit
+  private[simulator] def processBackends(
+    processor:                 Simulator.BackendProcessor,
+    commonCompilationSettings: CommonCompilationSettings
+  ): Unit
   private[simulator] def _simulate[T <: RawModule, U](
-    module: => T
-  )(body:   (SimulatedModule[T]) => U
+    module:       => T,
+    layerControl: LayerControl.Type
+  )(body:         (SimulatedModule[T]) => U
   ): Seq[Simulator.BackendInvocationDigest[U]] = {
     val workspace = new Workspace(path = workspacePath, workingDirectoryPrefix = workingDirectoryPrefix)
     workspace.reset()
@@ -120,7 +125,13 @@ trait Simulator {
         outcome
       }
     )
-    processBackends(compiler)
+
+    processBackends(
+      compiler,
+      commonCompilationSettings.copy(verilogPreprocessorDefines =
+        commonCompilationSettings.verilogPreprocessorDefines ++ layerControl.preprocessorDefines(elaboratedModule)
+      )
+    )
     compiler.results.toSeq
   }
 }
@@ -129,10 +140,11 @@ trait MultiBackendSimulator extends Simulator {
   def processBackends(processor: Simulator.BackendProcessor): Unit
 
   def simulate[T <: RawModule, U](
-    module: => T
-  )(body:   (SimulatedModule[T]) => U
+    module:       => T,
+    layerControl: LayerControl.Type = LayerControl.EnableAll
+  )(body:         (SimulatedModule[T]) => U
   ): Seq[Simulator.BackendInvocationDigest[U]] = {
-    _simulate(module)(body)
+    _simulate(module, layerControl)(body)
   }
 }
 
@@ -142,15 +154,19 @@ trait SingleBackendSimulator[T <: Backend] extends Simulator {
   def commonCompilationSettings:          CommonCompilationSettings
   def backendSpecificCompilationSettings: backend.CompilationSettings
 
-  final def processBackends(processor: Simulator.BackendProcessor): Unit = {
+  final def processBackends(
+    processor:                 Simulator.BackendProcessor,
+    commonCompilationSettings: CommonCompilationSettings
+  ): Unit = {
     processor.process(backend)(tag, commonCompilationSettings, backendSpecificCompilationSettings)
   }
 
   def simulate[T <: RawModule, U](
-    module: => T
-  )(body:   (SimulatedModule[T]) => U
+    module:       => T,
+    layerControl: LayerControl.Type = LayerControl.EnableAll
+  )(body:         (SimulatedModule[T]) => U
   ): Simulator.BackendInvocationDigest[U] = {
-    _simulate(module)(body).head
+    _simulate(module, layerControl)(body).head
   }
 
 }

src/test/scala/chiselTests/ChiselSpec.scala

@@ -61,7 +61,7 @@ trait ChiselRunners extends Assertions {
             VerilogPreprocessorDefine("ASSERT_VERBOSE_COND", s"!${Workspace.testbenchModuleName}.reset"),
             VerilogPreprocessorDefine("PRINTF_COND", s"!${Workspace.testbenchModuleName}.reset"),
             VerilogPreprocessorDefine("STOP_COND", s"!${Workspace.testbenchModuleName}.reset")
-          ),
+          ) ++ layerControl.preprocessorDefines(elaboratedModule),
           includeDirs = Some(Seq(workspace.primarySourcesPath)),
           fileFilter = layerControl.filter
         )

src/test/scala/chiselTests/simulator/EphemeraSimulatorSpec.scala

@@ -24,37 +24,81 @@ class EphemeralSimulatorSpec extends AnyFunSpec with Matchers {
       }
     }
     describe("layer control functionality") {
-      object A extends Layer(LayerConfig.Extract())
-      class Foo extends Module {
-        block(A) {
-          chisel3.assert(false.B)
+      describe("for extract layers") {
+        object A extends Layer(LayerConfig.Extract())
+        class Foo extends Module {
+          block(A) {
+            chisel3.assert(false.B)
+          }
         }
-      }
-      it("should enable all layers by default") {
-        intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
-          simulate(new Foo) { dut =>
-            dut.clock.step()
+        it("should enable all layers by default") {
+          intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
+            simulate(new Foo) { dut =>
+              dut.clock.step()
+            }
           }
         }
-      }
-      it("should enable all layers when provied with EnableAll") {
-        intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
-          simulate(new Foo, layerControl = LayerControl.EnableAll) { dut =>
+        it("should enable all layers when provied with EnableAll") {
+          intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
+            simulate(new Foo, layerControl = LayerControl.EnableAll) { dut =>
+              dut.clock.step()
+            }
+          }
+        }
+        it("should disable all layers when provided with Enable()") {
+          simulate(new Foo, layerControl = LayerControl.Enable()) { dut =>
             dut.clock.step()
           }
         }
-      }
-      it("should disable all layers when provided with Enable()") {
-        simulate(new Foo, layerControl = LayerControl.Enable()) { dut =>
-          dut.clock.step()
+        it("should enable specific layers with Enable") {
+          intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
+            simulate(new Foo, layerControl = LayerControl.Enable(A)) { dut =>
+              dut.clock.step()
+            }
+          }
         }
       }
-      it("should enable specific layers with Enable") {
-        intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
-          simulate(new Foo, layerControl = LayerControl.Enable(A)) { dut =>
+      describe("for inline layers") {
+        object A extends Layer(LayerConfig.Inline)
+        object B extends Layer(LayerConfig.Inline)
+        class Foo extends Module {
+          block(A) {
+            chisel3.assert(false.B)
+          }
+        }
+        it("should enable all layers by default") {
+          intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
+            simulate(new Foo) { dut =>
+              dut.clock.step()
+            }
+          }
+        }
+        it("should enable all layers when provied with EnableAll") {
+          intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
+            simulate(new Foo, layerControl = LayerControl.EnableAll) { dut =>
+              dut.clock.step()
+            }
+          }
+        }
+        it("should disable all layers when provided with Enable()") {
+          simulate(new Foo, layerControl = LayerControl.Enable()) { dut =>
             dut.clock.step()
           }
         }
+        it("should enable specific layers with Enable") {
+          intercept[svsim.Simulation.UnexpectedEndOfMessages.type] {
+            simulate(new Foo, layerControl = LayerControl.Enable(A)) { dut =>
+              dut.clock.step()
+            }
+          }
+        }
+        it("should error if an enabled layer does not exist") {
+          intercept[IllegalArgumentException] {
+            simulate(new Foo, layerControl = LayerControl.Enable(B)) { dut =>
+              dut.clock.step()
+            }
+          }.getMessage() must include("cannot enable layer 'B' as it is not one of the defined layers")
+        }
       }
     }
   }