Revert "remove DefRegInit, change DefReg API with option definition. …

[jackkoenig]

…(#1944)"

This reverts commit ed894c6.

The fix to #1944 isn't that complicated, but I'm opening this PR to note that currently master is broken if you're using the Emitter.

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• Did you add Scaladoc to every public function/method?
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Type of Improvement

API Impact

Backend Code Generation Impact

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[ekiwi]

Awesome. Let's get this in until we have a fix (which should also include a regression test so that we don;t miss something like this again).
Some of my stuff is failing locally, so getting this in would be awesome!

[sequencer]

Any CI to indicate which codes was broken by #1944? I'll try to fix that, and add corresponding tests.

[ekiwi]

Any CI to indicate which codes was broken by #1944? I'll try to fix that, and add corresponding tests.

In ip-contributions these tests failed: https://github.com/freechipsproject/ip-contributions/blob/729c253dcaf540be54dd65bd50567578b59e89d0/src/test/scala/chisel/lib/cordic/iterative/FixedCordicSpec.scala#L56

The error:

Elaborating design...
Done elaborating.
line 1123:37 mismatched input ':' expecting {'circuit', 'module', 'extmodule', 'input', 'output', 'UInt', 'SInt', 'Fixed', '.', 'Clock', 'Analog', '[', 'flip', 'parameter', 'reset', 'wire', 'reg', 'with', 'mem', 'cmem', 'smem', 'mport', 'inst', 'of', 'node', 'is', 'invalid', 'stop(', 'printf(', 'skip', 'attach', 'assert', 'assume', 'cover', 'depth', 'reader', 'writer', 'readwriter', 'when', 'else', 'infer', 'read', 'write', 'rdwr', 'old', 'new', 'undefined', 'mux(', 'validif(', 'stop', 'printf', 'mux', 'validif', 'add(', 'sub(', 'mul(', 'div(', 'rem(', 'lt(', 'leq(', 'gt(', 'geq(', 'eq(', 'neq(', 'pad(', 'asUInt(', 'asAsyncReset(', 'asSInt(', 'asClock(', 'asFixedPoint(', 'asInterval(', 'shl(', 'shr(', 'dshl(', 'dshr(', 'cvt(', 'neg(', 'not(', 'and(', 'or(', 'xor(', 'andr(', 'orr(', 'xorr(', 'cat(', 'bits(', 'head(', 'tail(', 'incp(', 'decp(', 'setp(', 'wrap(', 'clip(', 'squz(', FileInfo, Id, NEWLINE, DEDENT}
line 1572:4 mismatched input 'node' expecting {'circuit', 'module', 'extmodule', 'input', 'output', 'UInt', 'SInt', 'Fixed', '.', 'Clock', 'Analog', '[', 'flip', 'parameter', 'reset', 'wire', 'reg', 'with', 'mem', 'cmem', 'smem', 'mport', 'inst', 'of', 'node', 'is', 'invalid', 'stop(', 'printf(', 'skip', 'attach', 'assert', 'assume', 'cover', 'depth', 'reader', 'writer', 'readwriter', 'when', 'else', 'infer', 'read', 'write', 'rdwr', 'old', 'new', 'undefined', 'mux(', 'validif(', 'stop', 'printf', 'mux', 'validif', 'add(', 'sub(', 'mul(', 'div(', 'rem(', 'lt(', 'leq(', 'gt(', 'geq(', 'eq(', 'neq(', 'pad(', 'asUInt(', 'asAsyncReset(', 'asSInt(', 'asClock(', 'asFixedPoint(', 'asInterval(', 'shl(', 'shr(', 'dshl(', 'dshr(', 'cvt(', 'neg(', 'not(', 'and(', 'or(', 'xor(', 'andr(', 'orr(', 'xorr(', 'cat(', 'bits(', 'head(', 'tail(', 'incp(', 'decp(', 'setp(', 'wrap(', 'clip(', 'squz(', FileInfo, Id, NEWLINE, DEDENT}