Chisel v5.1.0

Features

• Fix color emission to check for interactive terminal (backport #3334) (by @mergify[bot] in #3336)
  • Chisel will now detect when it should print warnings, errors, and deprecations in color.
  • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
  • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
• Add support for Instantiate for BlackBox, ExtModule, and IntrinsicModule (backport #3349) (by @mergify[bot] in #3351)
• Add support for zero-width bit extraction (backport #3352) (by @mergify[bot] in #3354)
• Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #3228) (by @mergify[bot] in #3362)
  This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
• SRAM API: Add a parameter to initialize the memory (backport #3364) (by @mergify[bot] in #3380)
  SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
• Support literals and DontCare in DataView targets (backport #3389) (by @mergify[bot] in #3391)
• SRAM API: Add multiple-clocked port API (backport #3383) (by @mergify[bot] in #3405)
  Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
• Add support for configurable warnings (backport #3414) (by @mergify[bot] in #3431)
  Add support for configurable warnings, see https://www.chisel-lang.org/chisel3/docs/explanations/warnings.html
• Enrich ShiftRegister with SyncReadMem-based implementation. (backport #2891) (by @mergify[bot] in #3571)
  Supplement ShiftRegister with SyncReadMem-based implementation.
• Add --dump-fir option to ChiselStage (backport #3453) (by @mergify[bot] in #3456)
  This option will dump the .fir before invoking firtool.
  • Additional changes:
    • Use os.lib for invoking firtool
    • Use lazy serialization to avoid holding the entire FIRRTL in memory.
    • Mix NoStackTrace into FirtoolNotFound
    • Fix detection of no firtool

API Deprecation

• Deprecate calling .viewAs on non-hardware (backport #3395) (by @mergify[bot] in #3400)
  Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.

Performance

• Convert Vec dynamic index with a literal to static index (backport #3314) (by @mergify[bot] in #3319)
• Fix issue where reify would do the same lookup twice (backport #3392) (by @mergify[bot] in #3397)
• Optimize source locator escaping when emitting FIRRTL (backport #3439) (by @mergify[bot] in #3449)
  Only escape/unescape source locators that need it, avoids a String copy in the common case.

Fixes

• Gate sys/personality.h include under define (backport #3307) (by @mergify[bot] in #3308)
• Don't emit implicit clock warnings for SyncReadMem.readWrite when explicit clocks are used (backport #3313) (by @mergify[bot] in #3316)
• Make svsim shutdown gracefully when the test throws an exception (backport #3309) (by @mergify[bot] in #3310)
  • Fixed an issue where throwing an assert from an svsim simulation run may kill the simulated process before it can finish writing a waveform.
• Report Builder errors even when exception is thrown (backport #3341) (by @mergify[bot] in #3343)
  Chisel will to report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
• Add messages to require statements in Math (backport #3385) (by @mergify[bot] in #3388)
  • log2 functions
  • unsignedBitLength
• [svsim] Don't redirect simulation stderr to a pipe (backport #3403) (by @mergify[bot] in #3406)
  • Fixes an issue where simulations that logged to stderr could hang
• Sanitize Record._elements (backport #3419) (by @mergify[bot] in #3427)
  Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
• Restore BundleUpcastable (backport #3487) (by @mergify[bot] in #3494)
  Restore BundleUpcastable and deprecate it.
• Fix DataMirror.internal.chiselTypeClone to preserve Scala type (backport #3553) (by @mergify[bot] in #3555)
• Fix Decodetable (backport #3563) (by @mergify[bot] in #3580)
• Add type ascription to implicits from instantiable (backport #3615) (by @mergify[bot] in #3618)
  This fixes Scala compiler warnings in Scala 2.13.12 requiring type ascriptions on public implicit definitions.

Documentation

• Remove references to interval types from the website docs (backport #3345) (by @mergify[bot] in #3348)
  Fixes #3325
• Bring ToC and Menu into alignment, some minor cleanup within docs (backport #3346) (by @mergify[bot] in #3347)
  Fix #3322
• Changed Array to Seq in MuxLookup explantation (backport #3547) (by @mergify[bot] in #3550)

Dependency Updates

• Add Scala 2.13.11 and 2.12.18 to plugin cross versions (backport #3327) (by @mergify[bot] in #3330)
• Bump to firtool 1.43.0 (backport #3332) (by @mergify[bot] in #3333)
  See release notes for firtool 1.41.0, 1.42.0, and 1.43.0.
• Add support for Scala 2.13.12 to the compiler plugin (backport #3527) (by @mergify[bot] in #3530)

Build and Internal Changes

• [5.x] Enable MiMa for v5.0.0 (by @chiselbot in #3290)
• [CI] Update versions in CI Workflow (backport #3291) (by @mergify[bot] in #3292)
• upgrade mill to 0.11.0 (backport #3367) (by @mergify[bot] in #3407)

Full Changelog: v5.0.0...v5.1.0

Chisel v6.0.0-M3

Features

• Make it possible to illegalize .asUInt on OpaqueTypes (by @jackkoenig in #3344)
  Subclasses of OpaqueType can override errorOnAsUInt to make it an elaboration time error if .asUInt is called on an instance of the particular type (including when nested inside of an Aggregate). This closes a large loophole in the OpaqueType API.
• Add MuxCell intrinsics (by @uenoku in #3372)
  This commit adds new intrinsics (MuxCell2 and MuxCell4) to provide users a way to directly use 2-to-1 and 4-to-1 MUX cells in synthesis tools (currently synopsys and cadence are supported) from Chisel level. Appropriate pragmas will be annotated in output verilog. FIRRTL implementation is llvm/circt#5428
• SRAM API: Add a parameter to initialize the memory (by @jared-barocsi in #3364)
  SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
• Support literals and DontCare in DataView targets (by @jackkoenig in #3389)
• SRAM API: Add multiple-clocked port API (by @jared-barocsi in #3383)
  Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
• Add a new take method on Bits that returns the requested number (by @chick in #3402)
  take will accept an argument of zero and will return a zero-length UInt
• Add support for configurable warnings (by @jackkoenig in #3414)
  Add support for configurable warnings, see https://www.chisel-lang.org/chisel3/docs/explanations/warnings.html
• Support leading whitespace in --warn-conf-file (by @jackkoenig in #3438)
  • Also make line comments work on lines with filter-action pairs.
• Add FirtoolBinaryPath option (by @GeorgeLyon in #3434)
  • Add FirtoolBinaryPathOption to select a different firtool binary at runtime.
• Add --dump-fir option to ChiselStage (by @jackkoenig in #3453)
  This option will dump the .fir before invoking firtool.

• Additional changes:
  • Use os.lib for invoking firtool
  • Use lazy serialization to avoid holding the entire FIRRTL in memory.
  • Mix NoStackTrace into FirtoolNotFound
  • Fix detection of no firtool

• Add hook to invoke hardware generators at the end of elaboration. (by @mikeurbach in #3446)
• Initial properties package and Property type. (by @mikeurbach in #3425)
• Add support for Integer properties and conversion to FIRRTL. (by @mikeurbach in #3470)
  The Integer property type is defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Support connecting Properties. (by @mikeurbach in #3481)
  Property assignment is defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Add support for Property literals, starting with existing int types. (by @mikeurbach in #3482)
  Property literals are defined in FIRRTL spec version 3.1.0: https://github.com/chipsalliance/firrtl-spec/releases/tag/v3.1.0.
• Add support for String Property type and literal. (by @mikeurbach in #3490)
• Add support for sequences of Properties, including values. (by @jackkoenig in #3491)
• Add support for Class and Object on top of Properties. (by @mikeurbach in #3489)
• Support Optionality of implicit clock and reset (by @jackkoenig in #3496)
  • withClock, withReset, and withClockAndReset now have forms that take Option[Clock] and Option[Reset]

• Module.clockOption and Module.resetOption return Option[Clock] and Option[Reset]

• Add Boolean Property type (by @adkian-sifive in #3503)
  API Modification: Add Boolean support to Property API
• Implement CIRCT converter (by @SpriteOvO in #3466)
• Add Disable, a new API for disabling simulation constructs (by @jackkoenig in #3497)
  Disable is a new type that represents the concept of disabling a simulation construct. It is handled similarly to the implicit clock and reset except Disable is notionally a function of the current implicit reset. Its default value is "not has been reset", a two-state simulation-only construct that is 0 when simulation starts and only becomes 1 after reset has been asserted, and then de-asserted. Because Disable has simulation-only semantics, it is not a Data and can only be used by simulation-only APIs.

API Modification

• Error when calling .viewAs on non-hardware (by @jackkoenig in #3398)
• Add a new BaseType type that Data inherits, and use it for ports. (by @mikeurbach in #3429)
• Make LTL properties use Clock and Disable by default (by @jackkoenig in #3498)
  Properties in package chisel3.ltl will now be clocked and disabled by default (if there is an implicit clock and disable). Default disable is not hasBeenReset of the current implicit reset (if one exists). The clock and disable can be removed by setting them to None via withClock, withReset, and withDisable APIs.

API Deprecation

• Deprecate calling .viewAs on non-hardware (by @jackkoenig in #3395)
  Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.
• Deprecate old BoringUtils API (by @jared-barocsi in #3428)
  BoringUtils.bore(source, sinks), BoringUtils.addSource and BoringUtils.addSink are now deprecated in favor of the new BoringUtils APIs: BoringUtils.bore(source), BoringUtils.tap(source) ...

Backend Code Generation

• [codegen] Use FIRRTL 3.0.0 syntax (connect, invalidate, regreset, radix-encoded integer literals) (by @seldridge in #3188)
• [codegen] Emit literal identifiers for numeric ids (by @seldridge in #3374)
  Use FIRRTL 3.0.0 emission of literal identifiers when a Chisel name begins with a digit.
• Support bulk connection for const types (by @trilorez in #3384)
• Avoid emitting 'const const' for const vecs of const elements (by @trilorez in #3393)
  Multiple consecutive 'const' modifiers are no longer emitted when emitting a const vector of const elements.
• Update BoringUtils.bore to not add a port when boring from a port. (by @mikeurbach in #3411)
• update ChiselPlugin to name tuples (by @albertchen-sifive in #3436)
  The chisel plugin will now name wires that are part of tuples e.g. val x = (Wire(Bool()), Wire(Bool())) will generate wires with names x_1 and x_2

Performance

• Fix issue where reify would do the same lookup twice (by @jackkoenig in #3392)
• Optimize source locator escaping when emitting FIRRTL (by @jackkoenig in #3439)
  Only escape/unescape source locators that need it, avoids a String copy in the common case.
• Use Instantiate for LTL intrinsic instantiation (by @jackkoenig in #3499)
  This vastly reduces the IR size when using LTL properties

Fixes

• Correctly set ProbeInfo to None for Aggregate types on a probe.read (by @girishpai in #3382)
  Probe.read needs to return non-probe data to work with connection operators. Previous version of this was not handling aggregates correctly - this PR rectifies that.
• Add messages to require statements in Math (by @jackkoenig in #3385)
  • log2 functions
  • unsignedBitLength
• [svsim] Don't redirect simulation stderr to a pipe (by @GeorgeLyon in #3403)
  • Fixes an issue where simulations that logged to stderr could hang
• Sanitize Record._elements (by @jackkoenig in #3419)
  Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
• Extend constants in probe.force and probe.forceInitial methods. (by @debs-sifive in #3418)
  Properly extend forced values in probe.force and probe.forceInitial methods. Error out on unknown widths.
• Remove SourceLineNoCol (by @jackkoenig in #3433)
  Tweak emission of source locators in error messages to match format in emitting FIRRTL (removed the : between filename and line number).
• Remove intermediate wire creation from Boringutils Tap API (by @debs-sifive in #3441)
  Remove intermediate wire creation from...

Chisel v6.0.0-M2

Features

• Add Top-level parameterized reset type (by @mwachs5 in #3276)
  Add a HasParameterizedResetType to mix into Modules for their top level .reset
• Allow out-of-package svsim backend implementations (by @GeorgeLyon in #3306)
  • Allow users of chisel to specify their own svsim.Backend implementations outside of Chisel. This is useful since in-tree backends may not support all versions of the specified backend (and we don't necessarily want them to).
• Support ref types on interfaces (by @trilorez in #3301)
• Fix color emission to check for interactive terminal (by @jackkoenig in #3334)
  • Chisel will now detect when it should print warnings, errors, and deprecations in color.
  • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
  • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
• Unify recursive Data traversals into DataMirror (by @jared-barocsi in #3300)
• Add support for Instantiate for BlackBox, ExtModule, and IntrinsicModule (by @jackkoenig in #3349)
• Add support for zero-width bit extraction (by @jackkoenig in #3352)
• Add basic linear temporal logic assertions (by @fabianschuiki in #3337)
• Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (by @jared-barocsi in #3228)
  This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.

API Modification

• Create "tap" API for boring probe-type (non-synthesizable) ports (by @debs-sifive in #3237)
  Create "tap" API for boring probe-type (non-synthesizable) ports.
• BoringUtils writable tap (rwTap) API (by @debs-sifive in #3284)
  Add writable tap (rwTap) API to BoringUtils, which drills writable probe ports downwards only.
• Remove support for Scala 2.12 (by @jackkoenig in #3331)
  Chisel 5 was the last major version supporting Scala 2.12, please upgrade to Scala 2.13.

API Deprecation

• Warn on incorrect widths for Vec dynamic indexing (by @jackkoenig in #3321)

Backend Code Generation

• [codegen] Simpler FIRRTL Code for Reg w/o Reset (by @seldridge in #3280)

Performance

• Optimize BitPat equals, overlap, and cover (by @jackkoenig in #3285)
• Convert Vec dynamic index with a literal to static index (by @jackkoenig in #3314)

Fixes

• Gate sys/personality.h include under define (by @trilorez in #3307)
• Make svsim shutdown gracefully when the test throws an exception (by @GeorgeLyon in #3309)
  • Fixed an issue where throwing an assert from an svsim simulation run may kill the simulated process before it can finish writing a waveform.
• Don't emit implicit clock warnings for SyncReadMem.readWrite when explicit clocks are used (by @jared-barocsi in #3313)
• Report Builder errors even when exception is thrown (by @jackkoenig in #3341)
  Chisel will report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
• Support linking ref types on interfaces (by @trilorez in #3326)

Documentation

• [docs] Update website for 5.0, 6.0 and fix links (by @jackkoenig in #3274)
• Update roadmap. (by @gonsolo in #3295)
• Bring ToC and Menu into alignment, some minor cleanup within docs (by @mwachs5 in #3346)
  Fix #3322
• Remove references to interval types from the website docs (by @mwachs5 in #3345)
  Fixes #3325
• Update meeting time and versions in README (by @jackkoenig in #3356)

Dependency Updates

• Update scalacheck-1-15 to 3.2.14.0 (by @scala-steward in #3265)
• Update scalatest to 3.2.16 (by @scala-steward in #3299)
• Update sbt to 1.8.3 (by @scala-steward in #3298)
• Add Scala 2.13.11 and 2.12.18 to plugin cross versions (by @jackkoenig in #3327)
• Bump to firtool 1.43.0 (by @jackkoenig in #3332)
  See release notes for firtool 1.41.0, 1.42.0, and 1.43.0.
• Bump to Scala 2.13.11 (by @jackkoenig in #3358)

Build and Internal Changes

• SemanticDB requires private fields of case class to use "val" (by @jackkoenig in #3270)
• Update PULL_REQUEST_TEMPLATE.md (by @mwachs5 in #3279)
  Update PR template to be less comment-driven
• [CI] Update versions in CI Workflow (by @jackkoenig in #3291)
• Update ChiselRunners to use svsim (by @GeorgeLyon in #3147)
  • All ChiselRunner tests now use svsim when calling assertTester{Passes,Fails}
• Add tests for using DataView with ref types (by @trilorez in #3320)
• Update sbt to 1.9.0 (by @scala-steward in #3339)
• Update sbt-scalafix to 0.11.0 (by @scala-steward in #3338)
• Make devcontainer point to CIRCT top-of-tree instead of latest release (by @GeorgeLyon in #3360)
  • VSCode devcontainer now follows CIRCT top-of-tree rather than latest release

Full Changelog: v6.0.0-M1...v6.0.0-M2

Chisel v5.0.0

Features

• add MuxLookup.fromEnum (by @albertchen-sifive in #3071)
  add chisel3.util.MuxLookup.fromEnum
• Fix FIRRTL spec emission and bump to spec 1.2.0 (by @jackkoenig in #3094)
  Fix emission of FIRRTL spec in emitted .fir. Now emitting FIRRTL version 1.2.0.
• add curried MuxLookup.apply, deprecate old apply (by @albertchen-sifive in #3095)
  Add a new version of MuxLookup.apply that takes two parameter lists instead of one. This helps the scala compiler report better type errors.
• Introduce svsim, a low level library for simulating SystemVerilog using Verilator and VCS. (by @GeorgeLyon in #3121)
  Added svsim, a new library for compiling and controlling SystemVerilog simulations in Scala using Verilator or VCS.
• Add Simulator class for simulating Chisel modules with svsim (by @GeorgeLyon in #3136)
  • Added chisel3.simulator.Simulator for simulating Chisel modules with svsim
• Use %[[]] format for ChiselAnnotations (by @seldridge in #3141)
• Add EphemeralSimulator API (by @GeorgeLyon in #3142)
  • Introduce chisel3.simulator.EphemeralSimulator for ephemeral scenarios (such as scala-cli)
• [svsim] Add option to wait for a VCS license if one is unavailable (by @GeorgeLyon in #3149)
• intmodule exporting (by @darthscsi in #3148)
  Generate implementation-specific intirnsics.
• Implement typeName API for stable Module names (by @jared-barocsi in #3130)
  This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues
• More Circt intrinsic wrappers (IsX, PlusArgsTest, PlusArgsValue) (by @darthscsi in #2958)
  Add support for Circt intrinsics.
• Added .exclude to Connectable (by @azidar in #3172)
  Added .exclude mechanism on Connectable to enable never connecting to/from the marked fields using any connectable operator.
• Add an annotation for specifying module port conventions (by @rwy7 in #3030)
• Patch VecInit.fill(0) invocation to successfully compile and yield a zero-width Vec (by @jared-barocsi in #3171)
  Fix VecInit.fill(0) calls so that they compile and yield 0-width Vecs
• Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in #3214)
  SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
• Added more Connectable customization functions (backport #3227) (by @mergify[bot] in #3231)
  • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
• Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
• Added .as, a useful function on Connectable when users to upcast the Scala type.
• Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration
• Allow DataView of Reset <=> [UInt<1>, AsyncReset] (backport #3181) (by @mergify[bot] in #3259)
• Enable .viewAsSupertype to work on Records (backport #3267) (by @mergify[bot] in #3269)
  • Allow .viewAsSupertype to work on Records, with additional tests.

• Ensure that errors in DataView show the problematic fields in a deterministic order.

• Add Top-level parameterized reset type (backport #3276) (by @mergify[bot] in #3282)
  Add a HasParameterizedResetType to mix into Modules for their top level .reset

API Modification

• [chisel5] git subtree add FIRRTL (by @seldridge in #2982)
• [chisel5] Build FIRRTL in-tree, not published dependency (by @seldridge in #2983)
• [chisel5] Remove SFC Compiler from FIRRTL Subtree (by @seldridge in #2984)
• Removed innards and NotStrict for CompileOptions, and object Chisel (by @azidar in #3055)
  Removal of Chisel and the NotStrict compile options.
• Remove compile options everywhere in Chisel internals. (by @azidar in #3056)
  Removed CompileOptions trait and associated code, as it is now unnecessary.
• Remove LegacyModule and LegacyBlackBox (by @azidar in #3058)
  Removed LegacyModule and LegacyBlackBox. Users should instead now extend Module or BlackBox.
• [nfc] Remove two unused SFC annotations (by @seldridge in #3102)
• Remove ImplicitInvalidate (by @azidar in #3096)
  Remove ImplicitInvalidate - now users must explicitly assign DontCare to a module, at instantiation site, rather than this happening automatically because the module extended ImplicitInvalidate.
• Remove reflectivelyFindIO, its unused (by @azidar in #3106)
• Use %[[]] format for ChiselAnnotations (by @seldridge in #3141)
• Fix Printf macro to catch s-interpolator usages in Scala 2.13 (by @adkian-sifive in #3143)
  Fix issue with printf macro error checking to catch s-interpolator usages in Scala 2.13
• Remove _compatAutoWrapPorts no-op method (by @seldridge in #3164)
• Emit annotations in the .fir file (by @jackkoenig in #3180)
  • Annotations are now emitted in the .fir file instead of in an auxiliary .anno.json file.
  • Serialized FIRRTL is now spec v2.0.0

API Deprecation

• Deprecate ChiselStage$.elaborate (by @seldridge in #3160)
• Deprecate Scala 2.12 in Chisel 3.6 through the compiler plugin (by @jared-barocsi in #3146)
  Deprecate Scala 2.12 for Chisel 3.6 and later versions

Performance

• Make return value of Serializer.lazily lazy (by @jackkoenig in #3122)
  Reduce peak memory usage during .fir serialization by using lazy intermediate data structures.
• Optimize BitPat equals, overlap, and cover (backport #3285) (by @mergify[bot] in #3288)

Fixes

• Fix paper cut: bad message on calling litValue on Bundle containing DontCare (by @chick in #3043)
  There is now a better message when calling litValue on a Bundle that contains a DontCare
  that shows the Bundle and fields
• Disallow --target-dir in ChiselStage$ (by @seldridge in #3063)
• Remove deprecated CIRCT Options (by @seldridge in #3101)
• Detect bound hardware when processing record elements (by @adkian-sifive in #3037)
  Using bound hardware as an Element for a Record will now throw a better error message
• Actually fail on compilation errors and fix issue with older gcc versions (by @GeorgeLyon in #3132)
• Fix naming for RHS of named unapply expressions (by @jackkoenig in #3163)
  This results in previously unnamed signals receiving names from the compiler plugin.
• Report firtool version when firtool invocation errors (by @jackkoenig in #3174)
• Revert checks for size 0 Vecs in connections (backport #3215) (by @mergify[bot] in #3216)
• Fix Instantiate for Product parameters (backport #3210) (by @mergify[bot] in #3218)
  Instantiate previously erased type information for case classes and case objects which could result in incorrect behavior.

Documentation

• Fix broken cookbook link (by @mwachs5 in #3073)
  Fix broken link in the cookbook about resolving UInt index mismatches
• Update README, fix link to roadmap.md (by @jensengrey in #3091)
• Update README.md, fix scala version support badge (by @seanjensengrey in #3119)
• mdoc-ify intrinsic explanation (by @mwachs5 in #3152)
  Use mdoc to compile check the intrinsics explanation doc
• update website and explanations menus to match eachother (by @mwachs5 in #3154)
  [Website] Update Explanation Menus to align with eachother
• Fix three broken links in README.md Documentation section (by @aswaterman in #3166)
• [CI] Add Release Notes Automation (by @jackkoenig in #3170)
• Update README.md for Chisel 5 (by @jackkoenig in https://github.com/c...

Chisel v6.0.0-M1

Features

• Add ConstType and Const(...) API (by @debs-sifive in #3046)
  Adds Const() API to create ConstTypes, which denotes Data that holds a constant value.
• Implement read-write memory accessors for SyncReadMem (by @jared-barocsi in #3190)
  SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
• [Feature] Add Interface, ConformsTo for Separate Compilation (by @seldridge in #3199)
• Handle BoringUtils in Chisel, rather than in FIRRTL compiler (by @azidar in #3187)
  • Added a new BoringUtils.bore that is performed during Chisel elaboration, not via Annotations+CIRCT. Punched ports are accessible to the user via DataMirror. However, using these reflection APIs or calling .toDefinition will fully close a module, to ensure that subsequent boring fails (and thus getting all ports is never stale).
  • Added a skipPrefix to enable ignoring the last prefix value in the prefix name stack.
• API for probing internal signals (by @debs-sifive in #3088)
  Adds an API for probing internal signals.
• Add ClockGate intrinsic (by @fabianschuiki in #3209)
  Add support for the circt.clock_gate intrinsic.
• Added more Connectable customization functions (by @azidar in #3227)
  • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
• Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
• Added .as, a useful function on Connectable when users to upcast the Scala type.
• Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration
• Allow DataView of Reset <=> [UInt<1>, AsyncReset] (by @seldridge in #3181)
• [feature] Add properties to Interface (by @seldridge in #3238)
• Enable .viewAsSupertype to work on Records (by @mwachs5 in #3267)
  • Allow .viewAsSupertype to work on Records, with additional tests.

• Ensure that errors in DataView show the problematic fields in a deterministic order.

Fixes

• Revert checks for size 0 Vecs in connections (by @jackkoenig in #3215)
• Fix Instantiate for Product parameters (by @jackkoenig in #3210)
  Instantiate previously erased type information for case classes and case objects which could result in incorrect behavior.
• [bugfix] Fix naming module with Unit parameter (by @seldridge in #3263)

Documentation

• [docs] Fix README logo and update versions (by @jackkoenig in #3189)
• [fix] typo fix: chosen port of arbiter is not onehot but UInt (by @SihaoLiu in #3235)
  Just a oneline fix to the comment of Arbiter chosen port

Dependency Updates

• Bump firtool version to 1.40.0 (by @seldridge in #3226)
• Update sbt-ci-release to 1.5.12 (by @scala-steward in #3234)
• Update sbt-mima-plugin to 1.1.2 (by @scala-steward in #3145)
• Update scalacheck-1-14 to 3.2.11.0 (by @scala-steward in #3264)
• Update data-class to 0.2.6 (by @scala-steward in #3049)
• Update sbt-assembly to 2.1.1 (by @scala-steward in #3047)
• Update scopt to 4.1.0 (by @scala-steward in #3048)
• Update upickle to 3.1.0 (by @scala-steward in #3169)

Build and Internal Changes

• Remove PartialConnect (by @seldridge in #3185)
• Update Mergify for backporting to 5.x (by @jackkoenig in #3191)
• Add Chisel Scala CLI template and automation (by @jackkoenig in #3186)
  Add a new Chisel template for using Chisel with Scala CLI, and adds some automation for uploading versions of this template on tagged releases (or workflow dispatch).
• Add Data.findFirstTypeMismatch for better type checking (by @jackkoenig in #3201)
• Read previousVersions for bincompat checking from a file (by @jackkoenig in #3202)
  We can now simply append versions as they are released to project/previous-versions.txt on relevant release branches. build.sbt also now contains instructions are how to waive binary compatibility breakages.
• Enable push CI on all *.x branches (by @jackkoenig in #3222)
• Improve SyncReadMem.read, .readWrite (by @jared-barocsi in #3221)
• Add workflow to automatically update binary compatibility checks (by @jackkoenig in #3242)
• Add new workflow to fixup backports for release notes (by @jackkoenig in #3252)
  Improve backport automation so that release notes generation from backport PRs works properly.
• Update .scala-steward.conf (by @jackkoenig in #3266)
  Make the frequency a legal value (14 days).

Full Changelog: v5.0.0-RC2...v6.0.0-M1

Chisel v5.0.0-RC2

Features

• Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in #3214)
  SyncReadMem.readWrite(address, writeData, enabled, isWrite) explicitly generates a read-write port that supports both read and write access to the memory.
• Added more Connectable customization functions (backport #3227) (by @mergify[bot] in #3231)
  • Added .unsafe, a useful function on Connectable when users want a connection to "try its best but don't error".
  • Added .squeezeAllAs, a useful function on Connectable when users want a connection to always squeeze, as well as upcast if desired.
  • Added .as, a useful function on Connectable when users to upcast the Scala type.
  • Connectable's now register erroneous connections (e.g. out of scope, unwritable sinks) to throw at end of elaboration

Fixes

• Revert checks for size 0 Vecs in connections (backport #3215) (by @mergify[bot] in #3216)
• Fix Instantiate for Product parameters (backport #3210) (by @mergify[bot] in #3218)
  Instantiate previously erased type information for case classes and case objects which could result in incorrect behavior.

Documentation

• [docs] Fix README logo and update versions (backport #3189) (by @mergify[bot] in #3193)

Dependency Updates

• Bump firtool version to 1.40.0 (backport #3226) (by @mergify[bot] in #3229)

Build and Internal Changes

• Add Chisel Scala CLI template and automation (backport #3186) (by @mergify[bot] in #3194)
  Add a new Chisel template for using Chisel with Scala CLI, and adds some automation for uploading versions of this template on tagged releases (or workflow dispatch).
• Add Data.findFirstTypeMismatch for better type checking (backport #3201) (by @mergify[bot] in #3205)
• Read previousVersions for bincompat checking from a file (backport #3202) (by @mergify[bot] in #3208)
  We can now simply append versions as they are released to project/previous-versions.txt on relevant release branches. build.sbt also now contains instructions are how to waive binary compatibility breakages.
• Enable push CI on all *.x branches (backport #3222) (by @mergify[bot] in #3223)
• Improve SyncReadMem.read, .readWrite (backport #3221) (by @mergify[bot] in #3233)

Full Changelog: v5.0.0-RC1...v5.0.0-RC2

Chisel v5.0.0-RC1

Features

• Add EphemeralSimulator API (by @GeorgeLyon in #3142)
  • Introduce chisel3.simulator.EphemeralSimulator for ephemeral scenarios (such as scala-cli)
• [svsim] Add option to wait for a VCS license if one is unavailable (by @GeorgeLyon in #3149)
• intmodule exporting (by @darthscsi in #3148)
  Generate implementation-specific intirnsics.
• Implement typeName API for stable Module names (by @jared-barocsi in #3130)
  This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues
• More Circt intrinsic wrappers (IsX, PlusArgsTest, PlusArgsValue) (by @darthscsi in #2958)
  Add support for Circt intrinsics.
• Added .exclude to Connectable (by @azidar in #3172)
  Added .exclude mechanism on Connectable to enable never connecting to/from the marked fields using any connectable operator.
• Add an annotation for specifying module port conventions (by @rwy7 in #3030)
• Patch VecInit.fill(0) invocation to successfully compile and yield a zero-width Vec (by @jared-barocsi in #3171)
  Fix VecInit.fill(0) calls so that they compile and yield 0-width Vecs

API Modification

• Fix Printf macro to catch s-interpolator usages in Scala 2.13 (by @adkian-sifive in #3143)
  Fix issue with printf macro error checking to catch s-interpolator usages in Scala 2.13
• Remove _compatAutoWrapPorts no-op method (by @seldridge in #3164)
• Emit annotations in the .fir file (by @jackkoenig in #3180)
  • Annotations are now emitted in the .fir file instead of in an auxiliary .anno.json file.
  • Serialized FIRRTL is now spec v2.0.0

API Deprecation

• Deprecate ChiselStage$.elaborate (by @seldridge in #3160)
• Deprecate Scala 2.12 in Chisel 3.6 through the compiler plugin (by @jared-barocsi in #3146)
  Deprecate Scala 2.12 for Chisel 3.6 and later versions

Fixes

• Fix naming for RHS of named unapply expressions (by @jackkoenig in #3163)
  This results in previously unnamed signals receiving names from the compiler plugin.
• Report firtool version when firtool invocation errors (by @jackkoenig in #3174)

Documentation

• mdoc-ify intrinsic explanation (by @mwachs5 in #3152)
  Use mdoc to compile check the intrinsics explanation doc
• update website and explanations menus to match eachother (by @mwachs5 in #3154)
  [Website] Update Explanation Menus to align with eachother
• Fix three broken links in README.md Documentation section (by @aswaterman in #3166)
• [CI] Add Release Notes Automation (by @jackkoenig in #3170)
• Update README.md for Chisel 5 (by @jackkoenig in #3093)

Dependency Updates

• Bump to firtool 1.37.0 (by @jackkoenig in #3155)
• Bump to firtool 1.38.0 (by @jackkoenig in #3179)
  See firtool release notes.

Build and Internal Changes

• [CI] Revamp VecSpec (by @jackkoenig in #3159)
• Added definition identifiers (by @azidar in #3135)
• [CI] Require PRs to main to be labeled (by @jackkoenig in #3168)
• [CI] Install firtool in the publish step (by @jackkoenig in #3176)
• rewrite mill build scripts for chisel5. (by @sequencer in #3045)

Full Changelog: v5.0.0-M2...v5.0.0-RC1

Chisel v3.6.0

The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.

Try it out using this Scastie! Also check out the API Docs.

Highlights

• New implementation of the FIRRTL compiler
  • The new FIRRTL compiler has been rewritten using MLIR.
  • Faster, better SystemVerilog emission, and a growing open-source community.
  • This version was released against firtool v1.37.0.
• Refined connection semantics (#2806)
  • Flexible yet safe.
  • See the documentation.
• Paths in source locators (#2791)
  • Source locators now include a distinguishing path from the root of your workspace.
  • This enables errors that point to your specific line of Chisel from MFC.
• Error reporting that includes a source line and caret
  • This works both for errors detected during Chisel elaboration and during MFC compilation

Deprecations

Note that many more deprecations are coming before the release of 3.6.0.

• Compatibility mode (import Chisel._)
• The Scala FIRRTL Compiler (import firrtl._)
  • This includes custom annotations and transformations
• FixedPoint and related APIs
• Intervals and related APIs
• All public APIs in package chisel3.internal, these should never have been public
• group API
• chisel3.stage.ChiselStage, use circt.stage.ChiselStage instead
• forceName on components, MFC only supports forceName on module instances
• loadMemoryFromFile SFC Details (#2986)
• Protobuf emission
• CIRCTStage
• NoRunFirrtlCompilerAnnotation
• LegacyModule, LegacyBlackbox, and ImplicitInvalidate

For users who wish to continue using the Scala FIRRTL Compiler or other removed APIs for the time being, please see Migration Off Deprecated Features below.

Removals

Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):

• cloneType is now generated for Records, it is an error to implement cloneType manually
• MultiIOModule (use Module)
• Parenthesized forms of zero-arity methods (eg. .asUInt() is removed, use .asUInt)
• RawModule.getPorts and chisel3.getModulePorts
• stop with non-zero return code
• APIs expecting hardware Strings (printf, assert, and assume) will error if you use a Data in an s-interpolated String (s"..."), use cf"..." instead.

Performance Improvements

The MLIR FIRRTL Compiler is much faster than the Scala FIRRTL Compiler (3-7x). Users should should substantial speedups by switching to using MFC.

In addition, while there have been many performance improvements to Chisel itself included in the 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 22% and 5% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.

• Optimize internal _ids datastructure to reduce its size: #2866
• Avoid creating unnecessary clones: #2611
  • eg. IO(Input(UInt(8.W))) will now create only a single UInt object instead of 3
• Removed reflective naming which removes an iteration of all Data within a Module: #2562
• Removed TransitNames and thus 2 vars from every HasId: #2604
• Improve performance of ChiselEnum annotations (#2923)

Other Changes

• New warnings for mismatched widths in dynamic bit selection of UInts
• Add experimental Instantiate API for multiply instantiating modules
• Support generate structured decoder with DecodeTable
• SystemVerilog Parameters for BlackBoxes are now emitted in alphabetical order
• Several APIs were moved between packages inside of chisel3
  • eg. chisel3.experimental.ChiselEnum was moved to package chisel3
• CIRCT Intrinsics
• Tweak MuxLookup API and add MuxLookup.fromEnum

Migration from Chisel 3.5

3.6.0 includes everything from 3.5.6 and before. Some features are newly deprecated in 3.5.6 that are removed in 3.6.0. Please bump to 3.5.6 before attempting to upgrade to 3.6.0.

Migration Off Deprecated Features

All users are encouraged to stop using deprecated features and migrate to the MLIR FIRRTL Compiler; however this may be difficult for some users. For users who depend on deprecated features for which there is no obvious replacement, please reach out to the Chisel developers by filing an issue: https://github.com/chipsalliance/chisel3/issues.

For those who cannot migrate yet and would like to suppress warnings about moving off of the Scala FIRRTL Compiler, you can use Scala's configurable warning support, to suppress the specific warnings. The easiest way to do this is to add the following Scalac option to your build flow: -Wconf:msg=Importing from firrtl:s". This will silence the warnings telling you to move off of SFC.

Chisel v3.6.0-RC3

The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.

Try it out using this Scastie! Also check out the API Docs.

Highlights

• New implementation of the FIRRTL compiler
  • The new FIRRTL compiler has been rewritten using MLIR.
  • Faster, better SystemVerilog emission, and a growing open-source community.
  • This version was released against firtool v1.37.0.
• Refined connection semantics (#2806)
  • Flexible yet safe.
  • See the documentation.
• Paths in source locators (#2791)
  • Source locators now include a distinguishing path from the root of your workspace.
  • This enables errors that point to your specific line of Chisel from MFC.
• Error reporting that includes a source line and caret
  • This works both for errors detected during Chisel elaboration and during MFC compilation

Deprecations

Note that many more deprecations are coming before the release of 3.6.0.

• Compatibility mode (import Chisel._)
• The Scala FIRRTL Compiler (import firrtl._)
  • This includes custom annotations and transformations
• FixedPoint and related APIs
• Intervals and related APIs
• All public APIs in package chisel3.internal, these should never have been public
• group API
• chisel3.stage.ChiselStage, use circt.stage.ChiselStage instead
• forceName on components, MFC only supports forceName on module instances
• loadMemoryFromFile SFC Details (#2986)
• Protobuf emission
• CIRCTStage
• NoRunFirrtlCompilerAnnotation
• LegacyModule, LegacyBlackbox, and ImplicitInvalidate

For users who wish to continue using the Scala FIRRTL Compiler or other removed APIs for the time being, please see Migration Off Deprecated Features below.

Removals

Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):

• cloneType is now generated for Records, it is an error to implement cloneType manually
• MultiIOModule (use Module)
• Parenthesized forms of zero-arity methods (eg. .asUInt() is removed, use .asUInt)
• RawModule.getPorts and chisel3.getModulePorts
• stop with non-zero return code
• APIs expecting hardware Strings (printf, assert, and assume) will error if you use a Data in an s-interpolated String (s"..."), use cf"..." instead.

Performance Improvements

The MLIR FIRRTL Compiler is much faster than the Scala FIRRTL Compiler (3-7x). Users should should substantial speedups by switching to using MFC.

In addition, while there have been many performance improvements to Chisel itself included in the 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 22% and 5% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.

• Optimize internal _ids datastructure to reduce its size: #2866
• Avoid creating unnecessary clones: #2611
  • eg. IO(Input(UInt(8.W))) will now create only a single UInt object instead of 3
• Removed reflective naming which removes an iteration of all Data within a Module: #2562
• Removed TransitNames and thus 2 vars from every HasId: #2604
• Improve performance of ChiselEnum annotations (#2923)

Other Changes

• New warnings for mismatched widths in dynamic bit selection of UInts
• Add experimental Instantiate API for multiply instantiating modules
• Support generate structured decoder with DecodeTable
• SystemVerilog Parameters for BlackBoxes are now emitted in alphabetical order
• Several APIs were moved between packages inside of chisel3
  • eg. chisel3.experimental.ChiselEnum was moved to package chisel3
• CIRCT Intrinsics
• Tweak MuxLookup API and add MuxLookup.fromEnum

Migration from Chisel 3.5

3.6.0-RC3 includes everything from 3.5.6 and before. Some features are newly deprecated in 3.5.6 that are removed in 3.6.0-RC3. Please bump to 3.5.6 before attempting to upgrade to 3.6.0-RC3.

Migration Off Deprecated Features

All users are encouraged to stop using deprecated features and migrate to the MLIR FIRRTL Compiler; however this may be difficult for some users. For users who depend on deprecated features for which there is no obvious replacement, please reach out to the Chisel developers by filing an issue: https://github.com/chipsalliance/chisel3/issues.

For those who cannot migrate yet and would like to suppress warnings about moving off of the Scala FIRRTL Compiler, you can use Scala's configurable warning support, to suppress the specific warnings. The easiest way to do this is to add the following Scalac option to your build flow: -Wconf:msg=Importing from firrtl:s,msg=Importing from firrtl:s". This will silence the warnings telling you to move off of SFC.

Chisel v5.0.0-M2

Features

• add MuxLookup.fromEnum (by @albertchen-sifive in #3071)
  add chisel3.util.MuxLookup.fromEnum
• Fix FIRRTL spec emission and bump to spec 1.2.0 (by @jackkoenig in #3094)
  Fix emission of FIRRTL spec in emitted .fir. Now emitting FIRRTL version 1.2.0.
• add curried MuxLookup.apply, deprecate old apply (by @albertchen-sifive in #3095)
  Add a new version of MuxLookup.apply that takes two parameter lists instead of one. This helps the scala compiler report better type errors.
• Introduce svsim, a low level library for simulating SystemVerilog using Verilator and VCS. (by @GeorgeLyon in #3121)
  Added svsim, a new library for compiling and controlling SystemVerilog simulations in Scala using Verilator or VCS.
• Add Simulator class for simulating Chisel modules with svsim (by @GeorgeLyon in #3136)
  • Added chisel3.simulator.Simulator for simulating Chisel modules with svsim

API Modification

• Removed innards and NotStrict for CompileOptions, and object Chisel (by @azidar in #3055)
  Removal of Chisel and the NotStrict compile options.
• Remove compile options everywhere in Chisel internals. (by @azidar in #3056)
  Removed CompileOptions trait and associated code, as it is now unnecessary.
• Remove LegacyModule and LegacyBlackBox (by @azidar in #3058)
  Removed LegacyModule and LegacyBlackBox. Users should instead now extend Module or BlackBox.
• [nfc] Remove two unused SFC annotations (by @seldridge in #3102)
• Remove ImplicitInvalidate (by @azidar in #3096)
  Remove ImplicitInvalidate - now users must explicitly assign DontCare to a module, at instantiation site, rather than this happening automatically because the module extended ImplicitInvalidate.
• Remove reflectivelyFindIO, its unused (by @azidar in #3106)

Performance

• Make return value of Serializer.lazily lazy (by @jackkoenig in #3122)
  Reduce peak memory usage during .fir serialization by using lazy intermediate data structures.

Fixes

• Fix paper cut: bad message on calling litValue on Bundle containing DontCare (by @chick in #3043)
  There is now a better message when calling litValue on a Bundle that contains a DontCare
  that shows the Bundle and fields
• Disallow --target-dir in ChiselStage$ (by @seldridge in #3063)
• Remove deprecated CIRCT Options (by @seldridge in #3101)
• Detect bound hardware when processing record elements (by @adkian-sifive in #3037)
  Using bound hardware as an Element for a Record will now throw a better error message
• Actually fail on compilation errors and fix issue with older gcc versions (by @GeorgeLyon in #3132)

Documentation

• Fix broken cookbook link (by @mwachs5 in #3073)
  Fix broken link in the cookbook about resolving UInt index mismatches
• Update README, fix link to roadmap.md (by @jensengrey in #3091)
• Update README.md, fix scala version support badge (by @seanjensengrey in #3119)

Dependency Updates

• Bump CIRCT to 1.34.0 (by @seldridge in #3079)
• Bump to firtool 1.35.0 (by @jackkoenig in #3128)
  Bump to firtool 1.35.0, see release notes: https://github.com/llvm/circt/releases/tag/firtool-1.35.0
• Bump to firtool 1.36.0 (by @jackkoenig in #3133)
  Bump to firtool 1.36.0, see release notes: https://github.com/llvm/circt/releases/tag/firtool-1.36.0

Build and Internal Changes

• Let sbt-dynver control the SBT version (by @jackkoenig in #3064)
  Change SNAPSHOT versioning scheme to be derived from git describe --tag. SNAPSHOTs will now be unique per push to main.
• [CI] Do full unshallow clone for publish job (by @jackkoenig in #3069)
• Use -std=c++11 for Verilator 5.0 support (by @seldridge in #3066)
• Require unshallow clone to publish in SBT (by @jackkoenig in #3070)
• Release Chisel v5.0.0-M1 (by @jackkoenig in #3087)
• Simplify assertKnownWidth to Verilog test (by @seldridge in #3078)
• Add VSCode devcontainer config (by @GeorgeLyon in #3083)
  Added standard config for VSCode dev containers that can get developers up and running with just Docker and VSCode. To use, simply open the repo in VSCode and choose "Rebuild and Reopen in Container".
• More VSCode Devcontainer Improvements (by @GeorgeLyon in #3120)
• Add SBT aliases for formatting including SBT files (by @jackkoenig in #3125)
• Fix svsim to publish as part of unipublish (by @jackkoenig in #3127)
• [devcontainer] Use CIRCT full source bundle instead of git (by @GeorgeLyon in #3139)

Full Changelog: v5.0.0-M1...v5.0.0-M2