Add combinatorial examples

assets/project/comb_2000_16_16_0-vivado.yaml

@@ -0,0 +1,25 @@
+srcs:
+ - src/comb_2000_16_16_0/netlist_EMPTY.edif
+top: netlist_EMPTY
+name: comb_2000_16_16_0
+clocks:
+vendors:
+  xilinx:
+    - arty-a35t
+    - arty-a100t
+    - nexys-video
+    - xczu7ev
+# Known to fail from: https://github.com/chipsalliance/fpga-interchange-tests/issues/122
+# required_toolchains:
+#   - nextpnr-fpga-interchange-already-synth
+skip_toolchains:
+  - vivado
+  - yosys-vivado
+  - yosys-vivado-uhdm
+  - vpr
+  - vpr-fasm2bels
+  - nextpnr-xilinx
+  - nextpnr-xilinx-fasm2bels
+  - nextpnr-fpga-interchange
+  - nextpnr-fpga-interchange-already-synth
+  - nextpnr-fpga-interchange-experimental-already-synth

assets/project/comb_2000_16_16_0.yaml

@@ -0,0 +1,24 @@
+srcs:
+ - src/comb_2000_16_16_0/comb_2000_16_16_0.netlist
+top: netlist_EMPTY
+name: comb_2000_16_16_0
+clocks:
+vendors:
+  xilinx:
+    - arty-a35t
+    - arty-a100t
+    - nexys-video
+    - xczu7ev
+# Known to fail from: https://github.com/chipsalliance/fpga-interchange-tests/issues/122
+# required_toolchains:
+#   - nextpnr-fpga-interchange-already-synth
+skip_toolchains:
+  - vivado
+  - yosys-vivado
+  - yosys-vivado-uhdm
+  - vpr
+  - vpr-fasm2bels
+  - nextpnr-xilinx
+  - nextpnr-xilinx-fasm2bels
+  - nextpnr-fpga-interchange
+  - vivado-already-synth

assets/project/comb_3000_16_16_0-vivado.yaml

@@ -0,0 +1,25 @@
+srcs:
+ - src/comb_3000_16_16_0/netlist_EMPTY.edif
+top: netlist_EMPTY
+name: comb_3000_16_16_0
+clocks:
+vendors:
+  xilinx:
+    - arty-a35t
+    - arty-a100t
+    - nexys-video
+    - xczu7ev
+# Known to fail from: https://github.com/chipsalliance/fpga-interchange-tests/issues/122
+# required_toolchains:
+#   - nextpnr-fpga-interchange-already-synth
+skip_toolchains:
+  - vivado
+  - yosys-vivado
+  - yosys-vivado-uhdm
+  - vpr
+  - vpr-fasm2bels
+  - nextpnr-xilinx
+  - nextpnr-xilinx-fasm2bels
+  - nextpnr-fpga-interchange
+  - nextpnr-fpga-interchange-already-synth
+  - nextpnr-fpga-interchange-experimental-already-synth

assets/project/comb_3000_16_16_0.yaml

@@ -0,0 +1,24 @@
+srcs:
+ - src/comb_3000_16_16_0/comb_3000_16_16_0.netlist
+top: netlist_EMPTY
+name: comb_3000_16_16_0
+clocks:
+vendors:
+  xilinx:
+    - arty-a35t
+    - arty-a100t
+    - nexys-video
+    - xczu7ev
+# Known to fail from: https://github.com/chipsalliance/fpga-interchange-tests/issues/122
+# required_toolchains:
+#   - nextpnr-fpga-interchange-already-synth
+skip_toolchains:
+  - vivado
+  - yosys-vivado
+  - yosys-vivado-uhdm
+  - vpr
+  - vpr-fasm2bels
+  - nextpnr-xilinx
+  - nextpnr-xilinx-fasm2bels
+  - nextpnr-fpga-interchange
+  - vivado-already-synth

conf/requirements.txt

@@ -14,5 +14,6 @@ simplejson
 termcolor
 terminaltables
 yapf==0.31.0
-git+https://github.com/antmicro/edalize.git@fpga-tool-perf-custom_nextpnr#egg=edalize
+networkx
+git+https://github.com/antmicro/edalize.git@fpga-tool-perf-custom_nextpnr-fix-vivado#egg=edalize
 https://github.com/chipsalliance/f4pga/archive/de9ed1f3dba34d641c354bdb070232887254b142.zip#subdirectory=f4pga

src/comb_2000_16_16_0/constr/arty-100t.xdc

@@ -0,0 +1,67 @@
+set_property IOSTANDARD LVCMOS33 [get_ports in0]
+set_property IOSTANDARD LVCMOS33 [get_ports in1]
+set_property IOSTANDARD LVCMOS33 [get_ports in10]
+set_property IOSTANDARD LVCMOS33 [get_ports in11]
+set_property IOSTANDARD LVCMOS33 [get_ports in12]
+set_property IOSTANDARD LVCMOS33 [get_ports in13]
+set_property IOSTANDARD LVCMOS33 [get_ports in14]
+set_property IOSTANDARD LVCMOS33 [get_ports in15]
+set_property IOSTANDARD LVCMOS33 [get_ports in2]
+set_property IOSTANDARD LVCMOS33 [get_ports in3]
+set_property IOSTANDARD LVCMOS33 [get_ports in4]
+set_property IOSTANDARD LVCMOS33 [get_ports in5]
+set_property IOSTANDARD LVCMOS33 [get_ports in6]
+set_property IOSTANDARD LVCMOS33 [get_ports in7]
+set_property IOSTANDARD LVCMOS33 [get_ports in8]
+set_property IOSTANDARD LVCMOS33 [get_ports in9]
+set_property IOSTANDARD LVCMOS33 [get_ports out0]
+set_property IOSTANDARD LVCMOS33 [get_ports out1]
+set_property IOSTANDARD LVCMOS33 [get_ports out10]
+set_property IOSTANDARD LVCMOS33 [get_ports out11]
+set_property IOSTANDARD LVCMOS33 [get_ports out12]
+set_property IOSTANDARD LVCMOS33 [get_ports out13]
+set_property IOSTANDARD LVCMOS33 [get_ports out14]
+set_property IOSTANDARD LVCMOS33 [get_ports out15]
+set_property IOSTANDARD LVCMOS33 [get_ports out2]
+set_property IOSTANDARD LVCMOS33 [get_ports out3]
+set_property IOSTANDARD LVCMOS33 [get_ports out4]
+set_property IOSTANDARD LVCMOS33 [get_ports out5]
+set_property IOSTANDARD LVCMOS33 [get_ports out6]
+set_property IOSTANDARD LVCMOS33 [get_ports out7]
+set_property IOSTANDARD LVCMOS33 [get_ports out8]
+set_property IOSTANDARD LVCMOS33 [get_ports out9]
+
+set_property PACKAGE_PIN R10 [get_ports in0]
+set_property PACKAGE_PIN T10 [get_ports in1]
+set_property PACKAGE_PIN T9 [get_ports in10]
+set_property PACKAGE_PIN U13 [get_ports in11]
+set_property PACKAGE_PIN T13 [get_ports in12]
+set_property PACKAGE_PIN V14 [get_ports in13]
+set_property PACKAGE_PIN U14 [get_ports in14]
+set_property PACKAGE_PIN V11 [get_ports in15]
+set_property PACKAGE_PIN V10 [get_ports in2]
+set_property PACKAGE_PIN V12 [get_ports in3]
+set_property PACKAGE_PIN U12 [get_ports in4]
+set_property PACKAGE_PIN U11 [get_ports in5]
+set_property PACKAGE_PIN T11 [get_ports in6]
+set_property PACKAGE_PIN V17 [get_ports in7]
+set_property PACKAGE_PIN U16 [get_ports in8]
+set_property PACKAGE_PIN U18 [get_ports in9]
+set_property PACKAGE_PIN U17 [get_ports out0]
+set_property PACKAGE_PIN V16 [get_ports out1]
+set_property PACKAGE_PIN V15 [get_ports out10]
+set_property PACKAGE_PIN T16 [get_ports out11]
+set_property PACKAGE_PIN R16 [get_ports out12]
+set_property PACKAGE_PIN T15 [get_ports out13]
+set_property PACKAGE_PIN T14 [get_ports out14]
+set_property PACKAGE_PIN R15 [get_ports out15]
+set_property PACKAGE_PIN P15 [get_ports out2]
+set_property PACKAGE_PIN R17 [get_ports out3]
+set_property PACKAGE_PIN P17 [get_ports out4]
+set_property PACKAGE_PIN N16 [get_ports out5]
+set_property PACKAGE_PIN N15 [get_ports out6]
+set_property PACKAGE_PIN M17 [get_ports out7]
+set_property PACKAGE_PIN M16 [get_ports out8]
+set_property PACKAGE_PIN P18 [get_ports out9]
+
+set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets *]

src/comb_2000_16_16_0/constr/arty-a35t.xdc

@@ -0,0 +1,67 @@
+set_property IOSTANDARD LVCMOS33 [get_ports in0]
+set_property IOSTANDARD LVCMOS33 [get_ports in1]
+set_property IOSTANDARD LVCMOS33 [get_ports in10]
+set_property IOSTANDARD LVCMOS33 [get_ports in11]
+set_property IOSTANDARD LVCMOS33 [get_ports in12]
+set_property IOSTANDARD LVCMOS33 [get_ports in13]
+set_property IOSTANDARD LVCMOS33 [get_ports in14]
+set_property IOSTANDARD LVCMOS33 [get_ports in15]
+set_property IOSTANDARD LVCMOS33 [get_ports in2]
+set_property IOSTANDARD LVCMOS33 [get_ports in3]
+set_property IOSTANDARD LVCMOS33 [get_ports in4]
+set_property IOSTANDARD LVCMOS33 [get_ports in5]
+set_property IOSTANDARD LVCMOS33 [get_ports in6]
+set_property IOSTANDARD LVCMOS33 [get_ports in7]
+set_property IOSTANDARD LVCMOS33 [get_ports in8]
+set_property IOSTANDARD LVCMOS33 [get_ports in9]
+set_property IOSTANDARD LVCMOS33 [get_ports out0]
+set_property IOSTANDARD LVCMOS33 [get_ports out1]
+set_property IOSTANDARD LVCMOS33 [get_ports out10]
+set_property IOSTANDARD LVCMOS33 [get_ports out11]
+set_property IOSTANDARD LVCMOS33 [get_ports out12]
+set_property IOSTANDARD LVCMOS33 [get_ports out13]
+set_property IOSTANDARD LVCMOS33 [get_ports out14]
+set_property IOSTANDARD LVCMOS33 [get_ports out15]
+set_property IOSTANDARD LVCMOS33 [get_ports out2]
+set_property IOSTANDARD LVCMOS33 [get_ports out3]
+set_property IOSTANDARD LVCMOS33 [get_ports out4]
+set_property IOSTANDARD LVCMOS33 [get_ports out5]
+set_property IOSTANDARD LVCMOS33 [get_ports out6]
+set_property IOSTANDARD LVCMOS33 [get_ports out7]
+set_property IOSTANDARD LVCMOS33 [get_ports out8]
+set_property IOSTANDARD LVCMOS33 [get_ports out9]
+
+set_property PACKAGE_PIN R10 [get_ports in0]
+set_property PACKAGE_PIN T10 [get_ports in1]
+set_property PACKAGE_PIN T9 [get_ports in10]
+set_property PACKAGE_PIN U13 [get_ports in11]
+set_property PACKAGE_PIN T13 [get_ports in12]
+set_property PACKAGE_PIN V14 [get_ports in13]
+set_property PACKAGE_PIN U14 [get_ports in14]
+set_property PACKAGE_PIN V11 [get_ports in15]
+set_property PACKAGE_PIN V10 [get_ports in2]
+set_property PACKAGE_PIN V12 [get_ports in3]
+set_property PACKAGE_PIN U12 [get_ports in4]
+set_property PACKAGE_PIN U11 [get_ports in5]
+set_property PACKAGE_PIN T11 [get_ports in6]
+set_property PACKAGE_PIN V17 [get_ports in7]
+set_property PACKAGE_PIN U16 [get_ports in8]
+set_property PACKAGE_PIN U18 [get_ports in9]
+set_property PACKAGE_PIN U17 [get_ports out0]
+set_property PACKAGE_PIN V16 [get_ports out1]
+set_property PACKAGE_PIN V15 [get_ports out10]
+set_property PACKAGE_PIN T16 [get_ports out11]
+set_property PACKAGE_PIN R16 [get_ports out12]
+set_property PACKAGE_PIN T15 [get_ports out13]
+set_property PACKAGE_PIN T14 [get_ports out14]
+set_property PACKAGE_PIN R15 [get_ports out15]
+set_property PACKAGE_PIN P15 [get_ports out2]
+set_property PACKAGE_PIN R17 [get_ports out3]
+set_property PACKAGE_PIN P17 [get_ports out4]
+set_property PACKAGE_PIN N16 [get_ports out5]
+set_property PACKAGE_PIN N15 [get_ports out6]
+set_property PACKAGE_PIN M17 [get_ports out7]
+set_property PACKAGE_PIN M16 [get_ports out8]
+set_property PACKAGE_PIN P18 [get_ports out9]
+
+set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets *]

src/comb_2000_16_16_0/constr/nexys-video.xdc

@@ -0,0 +1,67 @@
+set_property IOSTANDARD LVCMOS33 [get_ports in0]
+set_property IOSTANDARD LVCMOS33 [get_ports in1]
+set_property IOSTANDARD LVCMOS33 [get_ports in10]
+set_property IOSTANDARD LVCMOS33 [get_ports in11]
+set_property IOSTANDARD LVCMOS33 [get_ports in12]
+set_property IOSTANDARD LVCMOS33 [get_ports in13]
+set_property IOSTANDARD LVCMOS33 [get_ports in14]
+set_property IOSTANDARD LVCMOS33 [get_ports in15]
+set_property IOSTANDARD LVCMOS33 [get_ports in2]
+set_property IOSTANDARD LVCMOS33 [get_ports in3]
+set_property IOSTANDARD LVCMOS33 [get_ports in4]
+set_property IOSTANDARD LVCMOS33 [get_ports in5]
+set_property IOSTANDARD LVCMOS33 [get_ports in6]
+set_property IOSTANDARD LVCMOS33 [get_ports in7]
+set_property IOSTANDARD LVCMOS33 [get_ports in8]
+set_property IOSTANDARD LVCMOS33 [get_ports in9]
+set_property IOSTANDARD LVCMOS33 [get_ports out0]
+set_property IOSTANDARD LVCMOS33 [get_ports out1]
+set_property IOSTANDARD LVCMOS33 [get_ports out10]
+set_property IOSTANDARD LVCMOS33 [get_ports out11]
+set_property IOSTANDARD LVCMOS33 [get_ports out12]
+set_property IOSTANDARD LVCMOS33 [get_ports out13]
+set_property IOSTANDARD LVCMOS33 [get_ports out14]
+set_property IOSTANDARD LVCMOS33 [get_ports out15]
+set_property IOSTANDARD LVCMOS33 [get_ports out2]
+set_property IOSTANDARD LVCMOS33 [get_ports out3]
+set_property IOSTANDARD LVCMOS33 [get_ports out4]
+set_property IOSTANDARD LVCMOS33 [get_ports out5]
+set_property IOSTANDARD LVCMOS33 [get_ports out6]
+set_property IOSTANDARD LVCMOS33 [get_ports out7]
+set_property IOSTANDARD LVCMOS33 [get_ports out8]
+set_property IOSTANDARD LVCMOS33 [get_ports out9]
+
+set_property PACKAGE_PIN N15 [get_ports in0]
+set_property PACKAGE_PIN R17 [get_ports in1]
+set_property PACKAGE_PIN P16 [get_ports in10]
+set_property PACKAGE_PIN N14 [get_ports in11]
+set_property PACKAGE_PIN N13 [get_ports in12]
+set_property PACKAGE_PIN R16 [get_ports in13]
+set_property PACKAGE_PIN P15 [get_ports in14]
+set_property PACKAGE_PIN P17 [get_ports in15]
+set_property PACKAGE_PIN N17 [get_ports in2]
+set_property PACKAGE_PIN T18 [get_ports in3]
+set_property PACKAGE_PIN R18 [get_ports in4]
+set_property PACKAGE_PIN R14 [get_ports in5]
+set_property PACKAGE_PIN P14 [get_ports in6]
+set_property PACKAGE_PIN U18 [get_ports in7]
+set_property PACKAGE_PIN U17 [get_ports in8]
+set_property PACKAGE_PIN AB18 [get_ports in9]
+set_property PACKAGE_PIN AA18 [get_ports out0]
+set_property PACKAGE_PIN W17 [get_ports out1]
+set_property PACKAGE_PIN V17 [get_ports out10]
+set_property PACKAGE_PIN AB20 [get_ports out11]
+set_property PACKAGE_PIN AA19 [get_ports out12]
+set_property PACKAGE_PIN V19 [get_ports out13]
+set_property PACKAGE_PIN V18 [get_ports out14]
+set_property PACKAGE_PIN Y19 [get_ports out15]
+set_property PACKAGE_PIN Y18 [get_ports out2]
+set_property PACKAGE_PIN W20 [get_ports out3]
+set_property PACKAGE_PIN W19 [get_ports out4]
+set_property PACKAGE_PIN V20 [get_ports out5]
+set_property PACKAGE_PIN U20 [get_ports out6]
+set_property PACKAGE_PIN AB22 [get_ports out7]
+set_property PACKAGE_PIN AB21 [get_ports out8]
+set_property PACKAGE_PIN Y22 [get_ports out9]
+
+set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets *]

src/comb_2000_16_16_0/constr/xczu7ev.xdc

@@ -0,0 +1,67 @@
+set_property IOSTANDARD LVCMOS18 [get_ports in0]
+set_property IOSTANDARD LVCMOS18 [get_ports in1]
+set_property IOSTANDARD LVCMOS18 [get_ports in10]
+set_property IOSTANDARD LVCMOS18 [get_ports in11]
+set_property IOSTANDARD LVCMOS18 [get_ports in12]
+set_property IOSTANDARD LVCMOS18 [get_ports in13]
+set_property IOSTANDARD LVCMOS18 [get_ports in14]
+set_property IOSTANDARD LVCMOS18 [get_ports in15]
+set_property IOSTANDARD LVCMOS18 [get_ports in2]
+set_property IOSTANDARD LVCMOS18 [get_ports in3]
+set_property IOSTANDARD LVCMOS18 [get_ports in4]
+set_property IOSTANDARD LVCMOS18 [get_ports in5]
+set_property IOSTANDARD LVCMOS18 [get_ports in6]
+set_property IOSTANDARD LVCMOS18 [get_ports in7]
+set_property IOSTANDARD LVCMOS18 [get_ports in8]
+set_property IOSTANDARD LVCMOS18 [get_ports in9]
+set_property IOSTANDARD LVCMOS18 [get_ports out0]
+set_property IOSTANDARD LVCMOS18 [get_ports out1]
+set_property IOSTANDARD LVCMOS18 [get_ports out10]
+set_property IOSTANDARD LVCMOS18 [get_ports out11]
+set_property IOSTANDARD LVCMOS18 [get_ports out12]
+set_property IOSTANDARD LVCMOS18 [get_ports out13]
+set_property IOSTANDARD LVCMOS18 [get_ports out14]
+set_property IOSTANDARD LVCMOS18 [get_ports out15]
+set_property IOSTANDARD LVCMOS18 [get_ports out2]
+set_property IOSTANDARD LVCMOS18 [get_ports out3]
+set_property IOSTANDARD LVCMOS18 [get_ports out4]
+set_property IOSTANDARD LVCMOS18 [get_ports out5]
+set_property IOSTANDARD LVCMOS18 [get_ports out6]
+set_property IOSTANDARD LVCMOS18 [get_ports out7]
+set_property IOSTANDARD LVCMOS18 [get_ports out8]
+set_property IOSTANDARD LVCMOS18 [get_ports out9]
+
+set_property PACKAGE_PIN F6 [get_ports in0]
+set_property PACKAGE_PIN E5 [get_ports in1]
+set_property PACKAGE_PIN D6 [get_ports in10]
+set_property PACKAGE_PIN D5 [get_ports in11]
+set_property PACKAGE_PIN B5 [get_ports in12]
+set_property PACKAGE_PIN A5 [get_ports in13]
+set_property PACKAGE_PIN F5 [get_ports in14]
+set_property PACKAGE_PIN F4 [get_ports in15]
+set_property PACKAGE_PIN E4 [get_ports in2]
+set_property PACKAGE_PIN D4 [get_ports in3]
+set_property PACKAGE_PIN C4 [get_ports in4]
+set_property PACKAGE_PIN B4 [get_ports in5]
+set_property PACKAGE_PIN C3 [get_ports in6]
+set_property PACKAGE_PIN B3 [get_ports in7]
+set_property PACKAGE_PIN D2 [get_ports in8]
+set_property PACKAGE_PIN C2 [get_ports in9]
+set_property PACKAGE_PIN H8 [get_ports out0]
+set_property PACKAGE_PIN G8 [get_ports out1]
+set_property PACKAGE_PIN H7 [get_ports out10]
+set_property PACKAGE_PIN G7 [get_ports out11]
+set_property PACKAGE_PIN H6 [get_ports out12]
+set_property PACKAGE_PIN G6 [get_ports out13]
+set_property PACKAGE_PIN J7 [get_ports out14]
+set_property PACKAGE_PIN J6 [get_ports out15]
+set_property PACKAGE_PIN K9 [get_ports out2]
+set_property PACKAGE_PIN J9 [get_ports out3]
+set_property PACKAGE_PIN L8 [get_ports out4]
+set_property PACKAGE_PIN K8 [get_ports out5]
+set_property PACKAGE_PIN M10 [get_ports out6]
+set_property PACKAGE_PIN L10 [get_ports out7]
+set_property PACKAGE_PIN M9 [get_ports out8]
+set_property PACKAGE_PIN M8 [get_ports out9]
+
+set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets *]