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Commit 9505d87

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fix
1 parent 6e1e785 commit 9505d87

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2 files changed

+5
-5
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2 files changed

+5
-5
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src/main/scala/subsystem/BaseSubsystem.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ trait HasConfigurablePRCILocations { this: HasPRCILocations =>
5757
val prciClockNode = ClockAdapterNode()
5858
val io_clocks = Option.when(p(SubsystemDriveClockFromIO)){
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val source = ClockSourceNode(Seq(ClockSourceParameters()))
60-
prciClockNode :*= source
60+
prciClockNode :*= FixedClockBroadcast() := source
6161
InModuleBody(source.makeIOs())
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}
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}
@@ -90,7 +90,7 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
9090

9191
val busContextName = "subsystem"
9292

93-
viewpointBus.clockNode := prciClockNode
93+
viewpointBus.clockNode :*= prciClockNode
9494

9595
// TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding
9696
// a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS.

src/main/scala/tilelink/BusWrapper.scala

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
3636
with HasTLBusParams
3737
with CanHaveBuiltInDevices
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{
39-
val clockNode = ClockAdapterNode() // device clocks attach here
39+
val clockNode = ClockIdentityNode() // device clocks attach here
4040
val fixedClockNode = FixedClockBroadcast(fixedClockOpt)
4141
private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt)))
4242

@@ -84,14 +84,14 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
8484
from(name) { gen(inwardNode :*=* TLNameNode("tl")) }
8585

8686
def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, asyncClockNode: ClockEphemeralNode): NoHandle = {
87-
bus.clockNode := asyncMux(xType, asyncClockNode, this.clockNode)
87+
bus.clockNode := asyncMux(xType, asyncClockNode, fixedClockNode)
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coupleTo(s"bus_named_${bus.busName}") {
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bus.crossInHelper(xType) :*= TLWidthWidget(beatBytes) :*= _
9090
}
9191
}
9292

9393
def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, asyncClockNode: ClockEphemeralNode): NoHandle = {
94-
this.clockNode := asyncMux(xType, asyncClockNode, bus.clockNode)
94+
this.clockNode := asyncMux(xType, asyncClockNode, bus.fixedClockNode)
9595
coupleFrom(s"bus_named_${bus.busName}") {
9696
_ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType)
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}

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