fix

Author: sequencer

src/main/scala/subsystem/BaseSubsystem.scala

@@ -57,7 +57,7 @@ trait HasConfigurablePRCILocations { this: HasPRCILocations =>
   val prciClockNode = ClockAdapterNode()
   val io_clocks = Option.when(p(SubsystemDriveClockFromIO)){
     val source = ClockSourceNode(Seq(ClockSourceParameters()))
-    prciClockNode :*= source
+    prciClockNode :*= FixedClockBroadcast() := source
     InModuleBody(source.makeIOs())
   }
 }

src/main/scala/subsystem/HasTiles.scala

@@ -268,18 +268,17 @@ trait CanAttachTile {
   def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
     implicit val p = context.p
     val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where)
+    // TODO: Handle it later
     (crossingParams.crossingType match {
       case _: SynchronousCrossing | _: CreditedCrossing =>
         if (crossingParams.forceSeparateClockReset) {
-          domain.clockNode := tlBusToGetClockDriverFrom.clockNode
+          domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
         } else {
           domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
         }
-      case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode
+      case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
       case _: AsynchronousCrossing => {
-        val tileClockGroup = ClockGroup()
-        // tileClockGroup := context.allClockGroupsNode
-        domain.clockNode := tileClockGroup
+        domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
       }
     })
 

src/main/scala/tilelink/BusWrapper.scala

@@ -36,7 +36,7 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
     with HasTLBusParams
     with CanHaveBuiltInDevices
 {
-  val clockNode = ClockAdapterNode() // device clocks attach here
+  val clockNode = ClockIdentityNode() // device clocks attach here
   val fixedClockNode = FixedClockBroadcast(fixedClockOpt)
   private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt)))
 
@@ -84,14 +84,14 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici
     from(name) { gen(inwardNode :*=* TLNameNode("tl")) }
 
   def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, asyncClockNode: ClockEphemeralNode): NoHandle = {
-    bus.clockNode := asyncMux(xType, asyncClockNode, this.clockNode)
+    bus.clockNode := asyncMux(xType, asyncClockNode, fixedClockNode)
     coupleTo(s"bus_named_${bus.busName}") {
       bus.crossInHelper(xType) :*= TLWidthWidget(beatBytes) :*= _
     }
   }
 
   def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, asyncClockNode: ClockEphemeralNode): NoHandle = {
-    this.clockNode := asyncMux(xType, asyncClockNode, bus.clockNode)
+    this.clockNode := asyncMux(xType, asyncClockNode, bus.fixedClockNode)
     coupleFrom(s"bus_named_${bus.busName}") {
       _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType)
     }