The new decoder

.gitmodules

@@ -7,3 +7,9 @@
 [submodule "dependencies/chisel"]
 	path = dependencies/chisel
 	url = https://github.com/chipsalliance/chisel.git
+[submodule "dependencies/rvdecoderdb"]
+	path = dependencies/rvdecoderdb
+	url = https://github.com/sequencer/rvdecoderdb.git
+[submodule "dependencies/riscv-opcodes"]
+	path = dependencies/riscv-opcodes
+	url = https://github.com/riscv/riscv-opcodes.git

build.sc

@@ -5,6 +5,7 @@ import coursier.maven.MavenRepository
 import $file.dependencies.hardfloat.common
 import $file.dependencies.cde.common
 import $file.dependencies.chisel.build
+import $file.dependencies.rvdecoderdb.common
 import $file.common
 
 object v {
@@ -16,6 +17,8 @@ object v {
     "source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"),
   )
   val mainargs = ivy"com.lihaoyi::mainargs:0.5.0"
+  val oslib = ivy"com.lihaoyi::os-lib:0.9.1"
+  val upickle = ivy"com.lihaoyi::upickle:3.1.3"
   val json4sJackson = ivy"org.json4s::json4s-jackson:4.0.5"
   val scalaReflect = ivy"org.scala-lang:scala-reflect:${scala}"
   val sonatypesSnapshots = Seq(
@@ -79,6 +82,23 @@ trait CDE
   override def millSourcePath = os.pwd / "dependencies" / "cde" / "cde"
 }
 
+object rvdecoderdb extends RVDecoderDB
+
+trait RVDecoderDB
+  extends millbuild.dependencies.rvdecoderdb.common.RVDecoderDBJVMModule
+    with RocketChipPublishModule
+    with ScalaModule {
+
+  def scalaVersion: T[String] = T(v.scala)
+
+  def osLibIvy = v.oslib
+
+  def upickleIvy = v.upickle
+
+  override def millSourcePath = os.pwd / "dependencies" / "rvdecoderdb" / "rvdecoderdb"
+}
+
+
 object rocketchip extends Cross[RocketChip](v.chiselCrossVersions.keys.toSeq)
 
 trait RocketChip
@@ -104,6 +124,8 @@ trait RocketChip
 
   def cdeModule = cde
 
+  def rvdecoderdbModule = rvdecoderdb
+
   def mainargsIvy = v.mainargs
 
   def json4sJacksonIvy = v.json4sJackson

common.sc

@@ -45,11 +45,14 @@ trait RocketChipModule
   // should be cde/common.sc#CDEModule
   def cdeModule: ScalaModule
 
+  // should be dependencies/rvdecoderdb/common.sc#RVDecoderDB
+  def rvdecoderdbModule: ScalaModule
+
   def mainargsIvy: Dep
 
   def json4sJacksonIvy: Dep
 
-  override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, cdeModule)
+  override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, cdeModule, rvdecoderdbModule)
 
   override def ivyDeps = T(
     super.ivyDeps() ++ Agg(

src/main/scala/rocket/CustomInstructions.scala → src/main/scala/deprecate/rocket/CustomInstructions.scala

@@ -4,6 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3.util._
+import freechips.rocketchip.rocket._
 
 object CustomInstructions {
   def MNRET              = BitPat("b01110000001000000000000001110011")

src/main/scala/rocket/Decode.scala → src/main/scala/deprecate/rocket/Decode.scala

@@ -5,6 +5,7 @@ package freechips.rocketchip.rocket
 import chisel3._
 import chisel3.util.BitPat
 import chisel3.util.experimental.decode._
+import freechips.rocketchip.rocket._
 
 object DecodeLogic
 {

src/main/scala/rocket/IDecode.scala → src/main/scala/deprecate/rocket/IDecode.scala

@@ -7,6 +7,7 @@ import chisel3._
 import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util._
+import freechips.rocketchip.rocket._
 import Instructions._
 import CustomInstructions._
 

src/main/scala/rocket/Instructions.scala → src/main/scala/deprecate/rocket/Instructions.scala

@@ -4,6 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3.util._
+import freechips.rocketchip.rocket._
 
 /* make EXTENSIONS="rv_* rv64*" inst.chisel */