[VeriblePreProcessor][5]: White-spaces support in "VerilogPreprocess" class.#1376
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karimtera wants to merge 12 commits intochipsalliance:masterfrom
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[VeriblePreProcessor][5]: White-spaces support in "VerilogPreprocess" class.#1376karimtera wants to merge 12 commits intochipsalliance:masterfrom
karimtera wants to merge 12 commits intochipsalliance:masterfrom
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…o generate all variants with the new mode generate-variants
…ass for the moment.
"verible::CmdPositionalArguments" class only supports these types so far: SV files, +define+<name>[=<value>], and +incdir+<dir>.
- Added a feature to VerilogPreprocess which allows to store paths, That can be used later to find the SV file to include. - The preprocessor tool takes these paths from the user, as a +incdir+<path>[+<another_path>] and set then in VerilogPreprocess. - The included files macros and conditionals can be expanded and evaluated. - Some limitations exists and were written as TODOs in place, need to open issues for these.
- The preprocessor tool preserves the white-spaces in the SV files. - Changed the output of the -generate_variants and -multipecu from tokens (enum,text) into normal text.
karimtera
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@kbieganski : this is a pull request that @karimtera started in the GSoC time. |
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NOTE: This is a part of the sequentially splitted PRs from PR #1360.
Description:
-generate_variantsand-multipe_cufrom tokens (enum, text) into normal text.