Add inlay hint support for Verilog module instantiations

[ya-uhs]

Summary

Add LSP inlay hint support to display port direction (input/output/inout) and type information for named port connections in module instantiations.

Example

For code like:

module child(input clk, input [7:0] data, output valid);
endmodule

module top;
  child inst (
    .clk(sys_clk),
    .data(bus_data),
    .valid(is_valid)
  );
endmodule

The editor will display hints like:

Changes

• Add inlay-hint.cc and inlay-hint.h implementing GenerateInlayHints()
• Register textDocument/inlayHint handler in verilog-language-server.cc
• Add inlayHintProvider capability
• Add tests for inlay hint functionality

Testing

• Added 3 test cases in verilog-language-server_test.cc:
  • InlayHintEmptyWhenModuleNotFound - returns empty when module not in symbol table
  • InlayHintEmptyForSimpleModule - returns empty when no instantiations
  • InlayHintWithModuleDefinition - returns hints with correct direction info

All existing tests pass.

[linux-foundation-easycla]

The committers listed above are authorized under a signed CLA.

• ✅ login: ya-uhs / name: shu (07cbfc7, 416e684, 7332dfc, fbf7ca6)