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kgugalakgugala
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Merge pull request #376 from antmicro/pcza/ql-qlf-k6n10f-asymmetric-ram
ql-qlf: k6n10f: add asymmetric RAM inference
2 parents ebd8fa8 + f680e2a commit 65ac65e

16 files changed

+2014
-34
lines changed

‎ql-qlf-plugin/Makefile‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,10 +23,13 @@ SOURCES = synth_quicklogic.cc \
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ql-dsp-simd.cc \
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ql-dsp-macc.cc \
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ql-bram-split.cc \
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ql-dsp-io-regs.cc
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ql-dsp-io-regs.cc \
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ql-bram-asymmetric.cc
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DEPS = pmgen/ql-dsp-pm.h \
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pmgen/ql-dsp-macc.h
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pmgen/ql-dsp-macc.h \
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pmgen/ql-bram-asymmetric-wider-write.h \
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pmgen/ql-bram-asymmetric-wider-read.h
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include ../Makefile_plugin.common
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@@ -85,6 +88,12 @@ pmgen/ql-dsp-pm.h: ../pmgen.py ql_dsp.pmg | pmgen
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pmgen/ql-dsp-macc.h: ../pmgen.py ql-dsp-macc.pmg | pmgen
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python3 ../pmgen.py -o $@ -p ql_dsp_macc ql-dsp-macc.pmg
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pmgen/ql-bram-asymmetric-wider-write.h: ../pmgen.py ql-bram-asymmetric-wider-write.pmg | pmgen
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python3 ../pmgen.py -o $@ -p ql_bram_asymmetric_wider_write ql-bram-asymmetric-wider-write.pmg
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pmgen/ql-bram-asymmetric-wider-read.h: ../pmgen.py ql-bram-asymmetric-wider-read.pmg | pmgen
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python3 ../pmgen.py -o $@ -p ql_bram_asymmetric_wider_read ql-bram-asymmetric-wider-read.pmg
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install_modules: $(VERILOG_MODULES)
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$(foreach f,$^,install -D $(f) $(DATA_DIR)/quicklogic/$(f);)
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‎ql-qlf-plugin/ql-bram-asymmetric-wider-read.pmg‎

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
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pattern ql_bram_asymmetric_wider_read
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state <SigSpec> mem_wr_data
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state <SigSpec> mem_wr_en
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state <SigSpec> mem_wr_addr
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state <SigSpec> mem_rd_data
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state <SigSpec> mem_rd_addr
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state <SigSpec> mux_ab
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state <SigSpec> mux_s
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state <SigSpec> mux_ba
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state <SigSpec> mux_input
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state <SigSpec> wr_data_shift_a
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state <SigSpec> wr_data_shift_b
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state <SigSpec> wr_en_and_a
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state <SigSpec> wr_en_and_b
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state <SigSpec> wr_en_and_y
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state <SigSpec> wr_en_shift_a
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state <SigSpec> wr_en_shift_b
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state <SigSpec> wr_en_shift_y
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match mem
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select mem->type == ($mem_v2)
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// 2 because it is a primary output connected to one cell (rq port or $shiftx cell)
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select nusers(port(mem, \WR_DATA)) == 2
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set mem_wr_data port(mem, \WR_DATA)
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set mem_wr_en port(mem, \WR_EN)
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set mem_wr_addr port(mem, \WR_ADDR)
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set mem_rd_data port(mem, \RD_DATA)
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set mem_rd_addr port(mem, \RD_ADDR)
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endmatch
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match wr_en_and
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select wr_en_and->type == ($and)
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set wr_en_and_a port(wr_en_and, \A)
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set wr_en_and_b port(wr_en_and, \B)
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set wr_en_and_y port(wr_en_and, \Y)
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endmatch
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match wr_en_shift
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select wr_en_shift->type.in($shl)
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set wr_en_shift_a port(wr_en_shift, \A)
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set wr_en_shift_b port(wr_en_shift, \B)
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set wr_en_shift_y port(wr_en_shift, \Y)
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endmatch
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match mux
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select mux->type == ($mux)
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choice <IdString> AB {\A, \B}
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(mux, \Y) === mem_wr_en
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index <SigSpec> port(mux, AB) === wr_en_shift_y
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set mux_ab port(mux, AB)
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set mux_s port(mux, \S)
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set mux_ba port(mux, BA)
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endmatch
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match wr_data_shift
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select wr_data_shift->type.in($shl)
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index <SigSpec> port(wr_data_shift, \Y) === mem_wr_data
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set wr_data_shift_a port(wr_data_shift, \A)
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set wr_data_shift_b port(wr_data_shift, \B)
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endmatch
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code
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accept;
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endcode

‎ql-qlf-plugin/ql-bram-asymmetric-wider-write.pmg‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
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pattern ql_bram_asymmetric_wider_write
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state <SigSpec> mem_rd_data
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state <SigSpec> mem_rd_addr
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state <SigSpec> mem_wr_data
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state <SigSpec> mem_wr_addr
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state <SigSpec> mem_wr_en
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state <SigSpec> rd_data_shift_y
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state <SigSpec> rd_data_ff_q
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state <SigSpec> rd_data_ff_en
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state <SigSpec> rd_data_ff_clk
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state <SigSpec> wr_addr_ff_d
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state <SigSpec> wr_en_mux_s
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state <SigSpec> rd_addr_and_a
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state <SigSpec> rd_addr_and_b
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match mem
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select mem->type == ($mem_v2)
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// 2 because it is a primary output connected to one cell (rq port or $shiftx cell)
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select nusers(port(mem, \RD_DATA)) == 2
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set mem_rd_data port(mem, \RD_DATA)
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set mem_rd_addr port(mem, \RD_ADDR)
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set mem_wr_data port(mem, \WR_DATA)
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set mem_wr_addr port(mem, \WR_ADDR)
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set mem_wr_en port(mem, \WR_EN)
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endmatch
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match rd_data_shift
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select rd_data_shift->type.in($shiftx)
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index <SigSpec> port(rd_data_shift, \A) === mem_rd_data
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set rd_data_shift_y port(rd_data_shift, \Y)
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endmatch
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match rd_data_ff
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select rd_data_ff->type.in($dffe)
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select nusers(port(rd_data_ff, \D)) == 2
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index <SigSpec> port(rd_data_ff, \D) === rd_data_shift_y
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set rd_data_ff_q port(rd_data_ff, \Q)
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set rd_data_ff_en port(rd_data_ff, \EN)
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set rd_data_ff_clk port(rd_data_ff, \CLK)
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endmatch
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match wr_addr_ff
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select wr_addr_ff->type.in($dff)
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select nusers(port(wr_addr_ff, \Q)) == 2
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index <SigSpec> port(wr_addr_ff, \Q) === mem_wr_addr
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set wr_addr_ff_d port(wr_addr_ff, \D)
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optional
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endmatch
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match wr_en_mux
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select wr_en_mux->type.in($mux)
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index <SigSpec> port(wr_en_mux, \Y) === mem_wr_en[0]
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set wr_en_mux_s port(wr_en_mux, \S)
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endmatch
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match rd_addr_and
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select rd_addr_and->type.in($and)
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set rd_addr_and_a port(rd_addr_and, \A)
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set rd_addr_and_b port(rd_addr_and, \B)
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endmatch
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code
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accept;
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endcode

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