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Commit 766239d

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mkurc-antmkurc-ant
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Fixed the way BRAM wires are identified, ensured unique inferred BRAM name.
Signed-off-by: Maciej Kurc <[email protected]>
1 parent da93173 commit 766239d

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3 files changed

+63
-42
lines changed

3 files changed

+63
-42
lines changed

‎ql-qlf-plugin/ql-bram-asymmetric.cc‎

Lines changed: 61 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -26,26 +26,37 @@ void test_ql_bram_asymmetric_wider_read(ql_bram_asymmetric_wider_read_pm &pm)
2626
auto wr_en_and_y = pm.st_ql_bram_asymmetric_wider_read.wr_en_and_y;
2727

2828
// Add the BRAM cell
29-
RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id("bram_asymmetric"), mem);
29+
std::string name = mem->name.str() + "$asymmetric";
30+
RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), mem);
3031

3132
// Set new type for cell so that it won't be processed by memory_bram pass
32-
cell->type = IdString("$mem_v2_asymmetric");
33+
cell->type = IdString(RTLIL::escape_id("_$_mem_v2_asymmetric"));
3334

3435
// Prepare wires from memory cell side to compare against module wires
35-
if (!mux_s.as_wire())
36-
log_error("WR_EN input wire not found");
36+
if (!mux_s.is_wire())
37+
log_error("WR_EN input wire not found\n");
3738
RTLIL::Wire *wr_en_cw = mux_s.as_wire();
38-
if (!mem_wr_addr.as_wire())
39-
log_error("WR_ADDR input wire not found");
40-
RTLIL::Wire *wr_addr_cw = mem_wr_addr.as_wire();
41-
if (!wr_data_shift_a.as_wire())
42-
log_error("WR_DATA input wire not found");
39+
40+
// The WR address wire can be narrower
41+
RTLIL::Wire *wr_addr_cw = nullptr;
42+
if (mem_wr_addr.is_wire())
43+
wr_addr_cw = mem_wr_addr.as_wire();
44+
else if (!mem_wr_addr.chunks().empty()) {
45+
auto chunk = mem_wr_addr.chunks()[0];
46+
if (chunk.is_wire())
47+
wr_addr_cw = chunk.wire;
48+
}
49+
if (!wr_addr_cw)
50+
log_error("WR_ADDR input wire not found\n");
51+
52+
if (!wr_data_shift_a.is_wire())
53+
log_error("WR_DATA input wire not found\n");
4354
RTLIL::Wire *wr_data_cw = wr_data_shift_a.as_wire();
44-
if (!mem_rd_addr.as_wire())
45-
log_error("RD_ADDR input wire not found");
55+
if (!mem_rd_addr.is_wire())
56+
log_error("RD_ADDR input wire not found\n");
4657
RTLIL::Wire *rd_addr_cw = mem_rd_addr.as_wire();
47-
if (!mem_rd_data.as_wire())
48-
log_error("RD_DATA input wire not found");
58+
if (!mem_rd_data.is_wire())
59+
log_error("RD_DATA input wire not found\n");
4960
RTLIL::Wire *rd_data_cw = mem_rd_data.as_wire();
5061

5162
// Check if wr_en_and cell has one of its inputs connected to write address
@@ -61,9 +72,9 @@ void test_ql_bram_asymmetric_wider_read(ql_bram_asymmetric_wider_read_pm &pm)
6172
wr_en_and_b_w = wr_en_and_b.as_wire();
6273
}
6374
if (!has_wire)
64-
log_error("RD_ADDR $and cell input wire not found");
65-
if ((wr_en_and_a_w != mem_wr_addr.as_wire()) & (wr_en_and_b_w != mem_wr_addr.as_wire()))
66-
log_error("This is not the $and cell we are looking for");
75+
log_error("RD_ADDR $and cell input wire not found\n");
76+
if ((wr_en_and_a_w != wr_addr_cw) & (wr_en_and_b_w != wr_addr_cw))
77+
log_error("This is not the $and cell we are looking for\n");
6778

6879
// Compare and assign wires
6980
RTLIL::Wire *wr_en_w = nullptr;
@@ -135,9 +146,9 @@ void test_ql_bram_asymmetric_wider_read(ql_bram_asymmetric_wider_read_pm &pm)
135146
}
136147

137148
if (wr_en_and_y != wr_en_shift_b.extract(offset, wr_addr_width))
138-
log_error("This is not the wr_en $shl cell we are looking for");
149+
log_error("This is not the wr_en $shl cell we are looking for\n");
139150
if (wr_en_and_y != wr_data_shift_b.extract(offset, wr_addr_width))
140-
log_error("This is not the wr_data $shl cell we are looking for");
151+
log_error("This is not the wr_data $shl cell we are looking for\n");
141152

142153
// Bypass shift on write address line
143154
cell->setPort(RTLIL::escape_id("WR_ADDR"), RTLIL::SigSpec(wr_addr_w));
@@ -178,10 +189,11 @@ void test_ql_bram_asymmetric_wider_write(ql_bram_asymmetric_wider_write_pm &pm)
178189
auto rd_addr_and_b = pm.st_ql_bram_asymmetric_wider_write.rd_addr_and_b;
179190

180191
// Add the BRAM cell
181-
RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id("bram_asymmetric"), mem);
192+
std::string name = mem->name.str() + "$asymmetric";
193+
RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), mem);
182194

183195
// Set new type for cell so that it won't be processed by memory_bram pass
184-
cell->type = IdString("$mem_v2_asymmetric");
196+
cell->type = IdString(RTLIL::escape_id("_$_mem_v2_asymmetric"));
185197

186198
// Prepare wires from memory cell side to compare against module wires
187199
RTLIL::Wire *rd_data_wc = nullptr;
@@ -191,17 +203,17 @@ void test_ql_bram_asymmetric_wider_write(ql_bram_asymmetric_wider_write_pm &pm)
191203
RTLIL::Wire *rd_addr_and_b_wc = nullptr;
192204

193205
if (rd_data_ff) {
194-
if (!rd_data_ff_q.as_wire())
195-
log_error("RD_DATA input wire not found");
206+
if (!rd_data_ff_q.is_wire())
207+
log_error("RD_DATA input wire not found\n");
196208
rd_data_wc = rd_data_ff_q.as_wire();
197-
if (!rd_data_ff_en.as_wire())
198-
log_error("RD_EN input wire not found");
209+
if (!rd_data_ff_en.is_wire())
210+
log_error("RD_EN input wire not found\n");
199211
rd_en_wc = rd_data_ff_en.as_wire();
200-
if (!rd_data_ff_clk.as_wire())
201-
log_error("RD_CLK input wire not found");
212+
if (!rd_data_ff_clk.is_wire())
213+
log_error("RD_CLK input wire not found\n");
202214
clk_wc = rd_data_ff_clk.as_wire();
203215
} else {
204-
log_error("output FF not found");
216+
log_error("output FF not found\n");
205217
}
206218

207219
if (rd_addr_and) {
@@ -215,27 +227,36 @@ void test_ql_bram_asymmetric_wider_write(ql_bram_asymmetric_wider_write_pm &pm)
215227
rd_addr_and_b_wc = rd_addr_and_b.as_wire();
216228
}
217229
if (!has_wire)
218-
log_error("RD_ADDR $and cell input wire not found");
230+
log_error("RD_ADDR $and cell input wire not found\n");
219231
} else {
220-
log_debug("RD_ADDR $and cell not found");
232+
log_debug("RD_ADDR $and cell not found\n");
221233
}
222234

223235
RTLIL::Wire *wr_addr_wc;
224236
if (wr_addr_ff) {
225-
if (!wr_addr_ff_d.as_wire())
226-
log_error("WR_ADDR input wire not found");
237+
if (!wr_addr_ff_d.is_wire())
238+
log_error("WR_ADDR input wire not found\n");
227239
wr_addr_wc = wr_addr_ff_d.as_wire();
228240
} else {
229-
if (!mem_wr_addr.as_wire())
230-
log_error("WR_ADDR input wire not found");
241+
if (!mem_wr_addr.is_wire())
242+
log_error("WR_ADDR input wire not found\n");
231243
wr_addr_wc = mem_wr_addr.as_wire();
232244
}
233245

234-
if (!mem_rd_addr.as_wire())
235-
log_error("RD_ADDR input wire not found");
236-
auto rd_addr_wc = mem_rd_addr.as_wire();
237-
if (!mem_wr_data.as_wire())
238-
log_error("WR_DATA input wire not found");
246+
// The RD address wire can be narrower
247+
RTLIL::Wire *rd_addr_wc = nullptr;
248+
if (mem_rd_addr.is_wire())
249+
rd_addr_wc = mem_rd_addr.as_wire();
250+
else if (!mem_rd_addr.chunks().empty()) {
251+
auto chunk = mem_rd_addr.chunks()[0];
252+
if (chunk.is_wire())
253+
rd_addr_wc = chunk.wire;
254+
}
255+
if (!rd_addr_wc)
256+
log_error("RD_ADDR input wire not found\n");
257+
258+
if (!mem_wr_data.is_wire())
259+
log_error("WR_DATA input wire not found\n");
239260
auto wr_data_wc = mem_wr_data.as_wire();
240261

241262
// Check if wr_en_and cell has one of its inputs connected to write address
@@ -309,7 +330,7 @@ void test_ql_bram_asymmetric_wider_write(ql_bram_asymmetric_wider_write_pm &pm)
309330

310331
// Connect Read Enable signal to memory cell
311332
if (!rd_en_w)
312-
log_error("Wire \\rce not found");
333+
log_error("Wire \\rce not found\n");
313334
auto rd_en_s = RTLIL::SigSpec(rd_en_w);
314335
cell->setPort(RTLIL::escape_id("RD_EN"), rd_en_s);
315336

@@ -322,7 +343,7 @@ void test_ql_bram_asymmetric_wider_write(ql_bram_asymmetric_wider_write_pm &pm)
322343
pm.module->remove(wr_addr_ff);
323344
// Check if detected $and is connected to RD_ADDR
324345
if ((rd_addr_and_a_wc != rd_addr_w) & (rd_addr_and_b_wc != rd_addr_w))
325-
log_error("This is not the $and cell we are looking for");
346+
log_error("This is not the $and cell we are looking for\n");
326347
else
327348
pm.module->remove(rd_addr_and);
328349
}

‎ql-qlf-plugin/qlf_k6n10f/brams_map.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -483,7 +483,7 @@ module \$__QLF_FACTOR_BRAM36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DA
483483
);
484484
endmodule
485485

486-
(* techmap_celltype = "$mem_v2_asymmetric" *)
486+
(* techmap_celltype = "_$_mem_v2_asymmetric" *)
487487
module \$__QLF_FACTOR_BRAM36_SDP_ASYMMETRIC (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, RD_EN, RD_SRST, WR_ADDR, WR_CLK, WR_DATA, WR_EN);
488488
parameter CFG_ABITS = 10;
489489
parameter CFG_DBITS = 36;

‎ql-qlf-plugin/qlf_k6n10f/cells_sim.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1507,7 +1507,7 @@ module BRAM2x18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA,
15071507
);
15081508
endmodule
15091509

1510-
module \$mem_v2_asymmetric (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, RD_EN, RD_SRST, WR_ADDR, WR_CLK, WR_DATA, WR_EN);
1510+
module \_$_mem_v2_asymmetric (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, RD_EN, RD_SRST, WR_ADDR, WR_CLK, WR_DATA, WR_EN);
15111511
localparam CFG_ABITS = 10;
15121512
localparam CFG_DBITS = 36;
15131513
localparam CFG_ENABLE_B = 4;

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