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tmichalaktmichalak
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Merge pull request #373 from antmicro/k6n10f-manual-dsps
[k6n10f] Preserve manually inserted DSPs
2 parents 65ac65e + ae7a729 commit da93173

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8 files changed

+53
-28
lines changed

8 files changed

+53
-28
lines changed

‎ql-qlf-plugin/ql-dsp-io-regs.cc‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,13 @@ struct QlDspIORegs : public Pass {
8282
std::string cell_type = cell.second->type.str();
8383
if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) {
8484
auto dsp = cell.second;
85+
86+
// If the cell does not have the "is_inferred" attribute set
87+
// then don't touch it.
88+
if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) || dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false) {
89+
continue;
90+
}
91+
8592
bool del_clk = true;
8693
bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3"));
8794

‎ql-qlf-plugin/ql-dsp-macc.cc‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,9 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
131131
// Add the DSP cell
132132
RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type);
133133

134+
// Set attributes
135+
cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true);
136+
134137
// Get input/output data signals
135138
RTLIL::SigSpec sig_a;
136139
RTLIL::SigSpec sig_b;

‎ql-qlf-plugin/ql-dsp-simd.cc‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -261,6 +261,15 @@ struct QlDspSimdPass : public Pass {
261261
simd->setParam(RTLIL::escape_id("MODE_BITS"), RTLIL::Const(mode_bits));
262262
log_assert(mode_bits.size() == mode_bits_size);
263263

264+
// Handle the "is_inferred" attribute. If one of the fragments
265+
// is not inferred mark the whole DSP as not inferred
266+
bool is_inferred_a =
267+
dsp_a->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_a->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false;
268+
bool is_inferred_b =
269+
dsp_b->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_b->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false;
270+
271+
simd->set_bool_attribute(RTLIL::escape_id("is_inferred"), is_inferred_a && is_inferred_b);
272+
264273
// Mark DSP parts for removal
265274
cellsToRemove.push_back(dsp_a);
266275
cellsToRemove.push_back(dsp_b);

‎ql-qlf-plugin/qlf_k6n10f/dsp_map.v‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y);
3434
{{(18 - B_WIDTH){1'b0}}, B};
3535

3636
generate if (`USE_DSP_CFG_PARAMS == 0) begin
37+
(* is_inferred=1 *)
3738
dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ (
3839
.a_i (a),
3940
.b_i (b),
@@ -53,6 +54,7 @@ module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y);
5354
.register_inputs_i (1'b0)
5455
);
5556
end else begin
57+
(* is_inferred=1 *)
5658
dsp_t1_20x18x64_cfg_params #(
5759
.OUTPUT_SELECT (3'd0),
5860
.SATURATE_ENABLE (1'b0),
@@ -98,6 +100,7 @@ module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y);
98100
{{( 9 - B_WIDTH){1'b0}}, B};
99101

100102
generate if (`USE_DSP_CFG_PARAMS == 0) begin
103+
(* is_inferred=1 *)
101104
dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ (
102105
.a_i (a),
103106
.b_i (b),
@@ -117,6 +120,7 @@ module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y);
117120
.register_inputs_i (1'b0)
118121
);
119122
end else begin
123+
(* is_inferred=1 *)
120124
dsp_t1_10x9x32_cfg_params #(
121125
.OUTPUT_SELECT (3'd0),
122126
.SATURATE_ENABLE (1'b0),

‎ql-qlf-plugin/tests/qlf_k6n10f/dsp_madd/dsp_madd.v‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,12 @@ module madd_simple_ports (
2323

2424
// There is no support for autmoatic inference of multiply+add hence the
2525
// DSP cell needs to be instanced manually.
26+
//
27+
// To test the type change the "is_inferred" attribute is set here
28+
// explicitily to mimic possible inference
2629

2730
// B * coeff[C] + A
31+
(* is_inferred=1 *)
2832
dsp_t1_10x9x32_cfg_ports # (
2933
.COEFF_0 (10'h011),
3034
.COEFF_1 (10'h022),
@@ -62,8 +66,12 @@ module madd_simple_params (
6266

6367
// There is no support for autmoatic inference of multiply+add hence the
6468
// DSP cell needs to be instanced manually.
69+
//
70+
// To test the type change the "is_inferred" attribute is set here
71+
// explicitily to mimic possible inference
6572

6673
// B * coeff[C] + A
74+
(* is_inferred=1 *)
6775
dsp_t1_10x9x32_cfg_params # (
6876
.COEFF_0 (10'h011),
6977
.COEFF_1 (10'h022),

‎ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl‎

Lines changed: 10 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,6 @@ proc test_dsp_cfg_ports {top expected_cell_suffix cells2match} {
4848
design -load postopt
4949
yosys cd ${top}
5050
select -assert-count ${cells2match} t:QL_DSP2${expected_cell_suffix}
51-
select -assert-count 0 t:QL_DSP2
5251
select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
5352
select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports
5453

@@ -71,7 +70,6 @@ proc test_dsp_cfg_params {top expected_cell_suffix cells2match} {
7170
design -load postopt
7271
yosys cd ${TOP}
7372
select -assert-count ${cells2match} t:QL_DSP3${expected_cell_suffix}
74-
select -assert-count 0 t:QL_DSP3
7573
select -assert-count 0 t:dsp_t1_10x9x32_cfg_params
7674
select -assert-count 0 t:dsp_t1_20x18x64_cfg_params
7775

@@ -87,18 +85,15 @@ proc test_dsp_cfg_params {top expected_cell_suffix cells2match} {
8785
# of the inference, eg. _MULT, _MACC_REGIN, MADD_REGIN_REGOUT
8886
proc test_dsp_cfg_conflict {top expected_cell_suffix} {
8987
set TOP ${top}
90-
set USE_DSP_CFG_PARAMS 1
88+
set USE_DSP_CFG_PARAMS 0
9189
design -load read
9290
hierarchy -top $TOP
9391
check_equiv ${TOP} ${USE_DSP_CFG_PARAMS}
9492
design -load postopt
9593
yosys cd ${TOP}
96-
select -assert-count 1 t:QL_DSP2${expected_cell_suffix}
97-
select -assert-count 1 t:QL_DSP3${expected_cell_suffix}
98-
select -assert-count 0 t:QL_DSP2
94+
select -assert-count 2 t:QL_DSP2${expected_cell_suffix}
9995
select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
10096
select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports
101-
select -assert-count 0 t:QL_DSP3
10297
select -assert-count 0 t:dsp_t1_10x9x32_cfg_params
10398
select -assert-count 0 t:dsp_t1_20x18x64_cfg_params
10499

@@ -111,12 +106,12 @@ yosys -import ;# ingest plugin commands
111106
read_verilog dsp_simd.v
112107
design -save read
113108

114-
test_dsp_cfg_ports "simd_mult_explicit_ports" "_MULT_REGIN" 1
115-
test_dsp_cfg_params "simd_mult_explicit_params" "_MULT_REGIN" 1
116-
test_dsp_cfg_ports "simd_mult_inferred" "_MULT" 1
117-
test_dsp_cfg_params "simd_mult_inferred" "_MULT" 1
118-
test_dsp_cfg_ports "simd_mult_odd_ports" "_MULT_REGIN" 2
119-
test_dsp_cfg_params "simd_mult_odd_params" "_MULT_REGIN" 2
120-
test_dsp_cfg_ports "simd_mult_conflict_ports" "_MULT_REGIN" 2
121-
test_dsp_cfg_conflict "simd_mult_conflict_config" "_MULT_REGIN"
109+
test_dsp_cfg_ports "simd_mult_explicit_ports" "" 1
110+
test_dsp_cfg_params "simd_mult_explicit_params" "" 1
111+
test_dsp_cfg_ports "simd_mult_inferred" "_MULT" 1
112+
test_dsp_cfg_params "simd_mult_inferred" "_MULT" 1
113+
test_dsp_cfg_ports "simd_mult_odd_ports" "" 2
114+
test_dsp_cfg_params "simd_mult_odd_params" "" 2
115+
test_dsp_cfg_ports "simd_mult_conflict_ports" "" 2
116+
test_dsp_cfg_conflict "simd_mult_conflict_config" ""
122117

‎ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.v‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -371,33 +371,32 @@ module simd_mult_conflict_config (
371371
output wire [15:0] z1
372372
);
373373

374-
dsp_t1_10x9x32_cfg_params #(
375-
.OUTPUT_SELECT (3'd0),
376-
.SATURATE_ENABLE (1'b0),
377-
.SHIFT_RIGHT (6'd0),
378-
.ROUND (1'b0),
379-
.REGISTER_INPUTS (1'b1)
380-
) dsp_0 (
374+
dsp_t1_10x9x32_cfg_ports dsp_0 (
381375
.a_i (a0),
382376
.b_i (b0),
383377
.z_o (z0),
384378

385-
.clock_i (clk),
379+
.clock_i (clk0),
386380

387381
.feedback_i (3'd0),
388382
.load_acc_i (1'b0),
389383
.unsigned_a_i (1'b1),
390384
.unsigned_b_i (1'b1),
391385

392-
.subtract_i (1'b0)
386+
.output_select_i (3'd0),
387+
.saturate_enable_i (1'b0),
388+
.shift_right_i (6'd0),
389+
.round_i (1'b0),
390+
.subtract_i (1'b0),
391+
.register_inputs_i (1'b0)
393392
);
394393

395394
dsp_t1_10x9x32_cfg_ports dsp_1 (
396395
.a_i (a1),
397396
.b_i (b1),
398397
.z_o (z1),
399398

400-
.clock_i (clk),
399+
.clock_i (clk1),
401400

402401
.feedback_i (3'd0),
403402
.load_acc_i (1'b0),
@@ -409,7 +408,7 @@ module simd_mult_conflict_config (
409408
.shift_right_i (6'd0),
410409
.round_i (1'b0),
411410
.subtract_i (1'b0),
412-
.register_inputs_i (1'b1)
411+
.register_inputs_i (1'b0)
413412
);
414413

415414
endmodule

‎ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd_post_synth_sim/dsp_simd_post_synth_sim.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ opt_expr -undriven
2424
opt_clean
2525
stat
2626
write_verilog sim/simd_mult_explicit_ports_post_synth.v
27-
select -assert-count 1 t:QL_DSP2_MULT_REGIN
27+
select -assert-count 1 t:QL_DSP2
2828

2929
select -clear
3030
design -load dsp_simd
@@ -35,4 +35,4 @@ opt_expr -undriven
3535
opt_clean
3636
stat
3737
write_verilog sim/simd_mult_explicit_params_post_synth.v
38-
select -assert-count 1 t:QL_DSP3_MULT_REGIN
38+
select -assert-count 1 t:QL_DSP3

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