systemverilog: simplify unions

tgorochowik · tgorochowik · commit 7a69cd855bed · 2022-08-03T12:35:18.000+02:00
The code for handling unions has been added together with the code for
structs, however it was never called due to a missing switch entry.

Signed-off-by: Tomasz Gorochowik &lt;tgorochowik@antmicro.com&gt;
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
@@ -937,6 +937,7 @@ static void simplify(AST::AstNode *current_node, AST::AstNode *parent_node)
         }
         break;
     case AST::AST_STRUCT:
+    case AST::AST_UNION:
         simplify_struct(current_node, 0, parent_node);
         // instance rather than just a type in a typedef or outer struct?
         if (!current_node->str.empty() && current_node->str[0] == '\\') {

Original file line number	Diff line number	Diff line change
`@@ -937,6 +937,7 @@ static void simplify(AST::AstNode current_node, AST::AstNode parent_node)`
`937`	`937`	`}`
`938`	`938`	`break;`
`939`	`939`	`case AST::AST_STRUCT:`
	`940`	`+ case AST::AST_UNION:`
`940`	`941`	`simplify_struct(current_node, 0, parent_node);`
`941`	`942`	`// instance rather than just a type in a typedef or outer struct?`
`942`	`943`	`if (!current_node->str.empty() && current_node->str[0] == '\\') {`