Merge pull request #344 from antmicro/separate-comp

Systemverilog: Add separate compilation flow

Author: rkapuscik

systemverilog-plugin/README.md

@@ -100,3 +100,18 @@ yosys> write_edif counter.edif
 
 ```
 As a result we get a `counter.edif` file that can be further processed to get the bitstream.
+
+### Parsing multiple files
+When parsing multiple files you can either pass them together to the `read_systemverilog` command
+or read them one by one using `-defer` flag. In the latter case, you will need to call 
+`readsystemverilog -link` after processing all files to elaborate them. An example flow would
+look like below:
+```
+plugin -i systemverilog
+# Read each file separately
+read_systemverilog -defer dut.sv
+read_systemverilog -defer top.sv
+# Finish reading files, elaborate the design
+read_systemverilog -link
+# Continue Yosys flow...
+```

systemverilog-plugin/tests/Makefile

@@ -14,9 +14,12 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-TESTS = counter break_continue
+TESTS = counter \
+		break_continue \
+		separate-compilation
 
 include $(shell pwd)/../../Makefile_test.common
 
 counter_verify = true
 break_continue_verify = $(call diff_test,break_continue,out)
+separate-compilation_verify = true

systemverilog-plugin/tests/separate-compilation/separate-compilation-buf.sv

@@ -0,0 +1,21 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module BUF (
+  input I,
+  output O
+);
+  assign O = I;
+endmodule;

systemverilog-plugin/tests/separate-compilation/separate-compilation-pkg.sv

@@ -0,0 +1,19 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+package pkg;
+  parameter BITS = 4;
+  parameter LOG2DELAY = 22;
+endpackage

systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl

@@ -0,0 +1,16 @@
+yosys -import
+if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
+yosys -import  ;# ingest plugin commands
+
+set TMP_DIR /tmp
+if { [info exists ::env(TMPDIR) ] } {
+  set TMP_DIR $::env(TMPDIR)
+}
+
+# Testing simple round-trip
+read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP).v
+read_systemverilog -odir $TMP_DIR/separate-compilation-test -link
+hierarchy
+write_verilog

systemverilog-plugin/tests/separate-compilation/separate-compilation.v

@@ -0,0 +1,31 @@
+// Copyright 2020-2022 F4PGA Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+module top (
+  input clk,
+  output [3:0] led
+);
+
+  wire bufg;
+  BUF bufgctrl (
+      .I(clk),
+      .O(bufg)
+  );
+  reg [pkg::BITS + pkg::LOG2DELAY-1 : 0] counter = 0;
+  always @(posedge bufg) begin
+    counter <= counter + 1;
+  end
+  assign led[3:0] = counter >> pkg::LOG2DELAY;
+endmodule

systemverilog-plugin/uhdmastshared.h

@@ -42,6 +42,14 @@ class UhdmAstShared
     // applies only to read_systemverilog command
     bool parse_only = false;
 
+    // Flag that determines whether we should defer the elaboration
+    // applies only to read_systemverilog command
+    bool defer = false;
+
+    // Flag that determines whether we should perform the elaboration now
+    // applies only to read_systemverilog command
+    bool link = false;
+
     // Top nodes of the design (modules, interfaces)
     std::unordered_map<std::string, AST::AstNode *> top_nodes;
 

systemverilog-plugin/uhdmcommonfrontend.cc

@@ -33,7 +33,7 @@ void UhdmCommonFrontend::print_read_options()
     log("        ignore assert() statements");
     log("\n");
     log("    -debug\n");
-    log("        alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
+    log("        alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2\n");
     log("\n");
     log("    -dump_ast1\n");
     log("        dump abstract syntax tree (before simplification)\n");
@@ -53,16 +53,17 @@ void UhdmCommonFrontend::print_read_options()
     log("    -dump_rtlil\n");
     log("        dump generated RTLIL netlist\n");
     log("\n");
-    log("    -yydebug\n");
-    log("        enable parser debug output\n");
-    log("\n");
     log("    -report [directory]\n");
     log("        write a coverage report for the UHDM file\n");
     log("\n");
     log("    -defer\n");
     log("        only read the abstract syntax tree and defer actual compilation\n");
     log("        to a later 'hierarchy' command. Useful in cases where the default\n");
     log("        parameters of modules yield invalid or not synthesizable code.\n");
+    log("        Needs to be followed by read_systemverilog -link after reading\n");
+    log("        all files.\n");
+    log("    -link\n");
+    log("        performs linking and elaboration of the files read with -defer\n");
     log("    -parse-only\n");
     log("        this parameter only applies to read_systemverilog command,\n");
     log("        it runs only Surelog to parse design, but doesn't load generated\n");
@@ -97,7 +98,7 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve
         } else if (args[i] == "-noassert") {
             this->shared.no_assert = true;
         } else if (args[i] == "-defer") {
-            defer = true;
+            this->shared.defer = true;
         } else if (args[i] == "-dump_ast1") {
             dump_ast1 = true;
         } else if (args[i] == "-dump_ast2") {
@@ -110,15 +111,20 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve
             no_dump_ptr = true;
         } else if (args[i] == "-dump_rtlil") {
             dump_rtlil = true;
-        } else if (args[i] == "-yydebug") {
-            this->shared.debug_flag = true;
         } else if (args[i] == "-parse-only") {
             this->shared.parse_only = true;
+        } else if (args[i] == "-link") {
+            this->shared.link = true;
+            // Surelog needs it in the command line to link correctly
+            unhandled_args.push_back(args[i]);
         } else {
             unhandled_args.push_back(args[i]);
         }
     }
-    extra_args(f, filename, args, args.size() - 1);
+    // Yosys gets confused when extra_args are passed with -link or no option
+    // It's done fully by Surelog, so skip it in this case
+    if (!this->shared.link)
+        extra_args(f, filename, args, args.size() - 1);
     // pass only unhandled args to Surelog
     // unhandled args starts with command name,
     // but Surelog expects args[0] to be program name

systemverilog-plugin/uhdmsurelogastfrontend.cc

@@ -108,9 +108,19 @@ struct UhdmSurelogAstFrontend : public UhdmCommonFrontend {
         // Force -parse flag settings even if it wasn't specified
         clp->setwritePpOutput(true);
         clp->setParse(true);
-        clp->setCompile(true);
-        clp->setElaborate(true);
         clp->fullSVMode(true);
+        clp->setCacheAllowed(true);
+        if (this->shared.defer) {
+            clp->setCompile(false);
+            clp->setElaborate(false);
+            clp->setSepComp(true);
+        } else {
+            clp->setCompile(true);
+            clp->setElaborate(true);
+        }
+        if (this->shared.link) {
+            clp->setLink(true);
+        }
 
         SURELOG::scompiler *compiler = nullptr;
         const std::vector<vpiHandle> uhdm_design = executeCompilation(symbolTable, errors, clp, compiler);
@@ -121,11 +131,6 @@ struct UhdmSurelogAstFrontend : public UhdmCommonFrontend {
             }
         }
 
-        UHDM::Serializer serializer;
-        UHDM::SynthSubset *synthSubset = new UHDM::SynthSubset(&serializer, this->shared.nonSynthesizableObjects, false);
-        synthSubset->listenDesigns(uhdm_design);
-        delete synthSubset;
-
         SURELOG::shutdown_compiler(compiler);
         delete clp;
         delete symbolTable;
@@ -136,6 +141,19 @@ struct UhdmSurelogAstFrontend : public UhdmCommonFrontend {
             return nullptr;
 
         UhdmAst uhdm_ast(this->shared);
+        if (this->shared.defer && !this->shared.link)
+            return nullptr;
+
+        // FIXME: SynthSubset annotation is incompatible with separate compilation
+        // `-defer` turns elaboration off, so check for it
+        // Should be called 1. for normal flow 2. after finishing with `-link`
+        if (!this->shared.defer) {
+            UHDM::Serializer serializer;
+            UHDM::SynthSubset *synthSubset = new UHDM::SynthSubset(&serializer, this->shared.nonSynthesizableObjects, false);
+            synthSubset->listenDesigns(uhdm_design);
+            delete synthSubset;
+        }
+
         AST::AstNode *current_ast = uhdm_ast.visit_designs(uhdm_design);
         if (!this->report_directory.empty()) {
             this->shared.report.write(this->report_directory);