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@tmichalak
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@tmichalak tmichalak commented Dec 31, 2021

This PR aims at solving issue #179
It is still WIP as all of the error messages have to be reviewed and tests covering theses conditions created.
Currently the error messages are in the following form:

pll.input.sdc:2: ERROR: create_clock: Found non-positive period value of -2.000000, periods must be positive and greater than zero.

mglb pushed a commit to antmicro/yosys-f4pga-plugins that referenced this pull request Apr 3, 2023
…les/uhdm-tests/ibex/ibex-d1aff2f

Bump uhdm-tests/ibex/ibex from `cfeef7e` to `d1aff2f`
@hzeller
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hzeller commented Apr 26, 2023

This PR looks like it was drying on the vine ?

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3 participants