Sobel filter on FPGA

System performance is a topic that has been extensively analyzed and optimized using conventional techniques. However, given the CPU frequency limitations of the last decades as well as the decay of Moore’s Law, innovative architectures have arisen in order to address the issue. FPGAs are a relatively new concept of programmable hardware logic that has been proposed to alleviate exactly this problem. They are to be used isolated as microcontrollers, or in embedded or larger, heterogeneous systems collaboratively with CPU as hardware accelerators. FPGA-based computing systems have been shown to provide superior performance for many application-specific computations in comparison to general-purpose architectures. This laboratory report is aiming in juxtaposing the performance optimization achieved using solely software techniques with a combination of software and hardware ones. A high-performance Sobel edge-detector acceleration core has been developed in Vivado HLS tool and compared to its counterpart: an extensively software optimized Sobel edge-detector application. Our results, which emphasize on the performance aspect, reveal the dominance of the core over the application.