RISC-V Superscalar CPU simulator

For full description of the project refer to final slides here

Useful links:

1. Design this project was inspired by: https://docs.boom-core.org/en/latest/sections/intro-overview/boom.html
2. Good explanation of load store queues: https://www.youtube.com/watch?v=IQP1dQ-rKP0
3. More information about explicit renaming: https://people.eecs.berkeley.edu/~kubitron/courses/cs252-S12/handouts/oldquiz/sp11-quiz1_soln.pdf
4. Explains bypass networks and detailed explanations of superscalar and dual issue: https://acg.cis.upenn.edu/milom/cis501-Fall11/lectures/07_superscalar.pdf#:~:text=Superscalar%20instruction%20register%20writeback%20One%20write%20port%20per,register%20Example%2C%204-wide%20superscalar%20%EF%83%A8%204%20write%20ports
5. pipeline flow page 37 :https://courses.cs.washington.edu/courses/cse471/07sp/lectures/Lecture4.pdf
6. step by step explanation of instruction flow: https://users.cs.utah.edu/~rajeev/cs6810/ooo.pdf