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Remove KnownDomain from Tutorial
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‎clash-prelude/src/Clash/Tutorial.hs

Lines changed: 82 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -1106,8 +1106,7 @@ import qualified Data.Vector as V
11061106
import GHC.Stack (HasCallStack, withFrozenCallStack)
11071107
11081108
blockRam#
1109-
:: ( KnownDomain dom
1110-
, HasCallStack
1109+
:: ( HasCallStack
11111110
, NFDataX a )
11121111
=> 'Clock' dom -- ^ 'Clock' to synchronize to
11131112
-> 'Enable' dom -- ^ Global enable
@@ -1154,40 +1153,39 @@ BlackBox:
11541153
kind: Declaration
11551154
type: |-
11561155
blockRam#
1157-
:: ( KnownDomain dom ARG[0]
1158-
, HasCallStack -- ARG[1]
1159-
, NFDataX a ) -- ARG[2]
1160-
=> Clock dom -- clk, ARG[3]
1161-
-> Enable dom -- en, ARG[4]
1162-
-> Vec n a -- init, ARG[5]
1163-
-> Signal dom Int -- rd, ARG[6]
1164-
-> Signal dom Bool -- wren, ARG[7]
1165-
-> Signal dom Int -- wr, ARG[8]
1166-
-> Signal dom a -- din, ARG[9]
1156+
:: ( HasCallStack -- ARG[0]
1157+
, NFDataX a ) -- ARG[1]
1158+
=> Clock dom -- clk, ARG[2]
1159+
-> Enable dom -- en, ARG[3]
1160+
-> Vec n a -- init, ARG[4]
1161+
-> Signal dom Int -- rd, ARG[5]
1162+
-> Signal dom Bool -- wren, ARG[6]
1163+
-> Signal dom Int -- wr, ARG[7]
1164+
-> Signal dom a -- din, ARG[8]
11671165
-> Signal dom a
11681166
template: |-
11691167
-- blockRam begin
11701168
~GENSYM[~RESULT_blockRam][1] : block
1171-
signal ~GENSYM[~RESULT_RAM][2] : ~TYP[5] := ~CONST[5];
1172-
signal ~GENSYM[rd][4] : integer range 0 to ~LENGTH[~TYP[5]] - 1;
1173-
signal ~GENSYM[wr][5] : integer range 0 to ~LENGTH[~TYP[5]] - 1;
1169+
signal ~GENSYM[~RESULT_RAM][2] : ~TYP[4] := ~CONST[4];
1170+
signal ~GENSYM[rd][4] : integer range 0 to ~LENGTH[~TYP[4]] - 1;
1171+
signal ~GENSYM[wr][5] : integer range 0 to ~LENGTH[~TYP[4]] - 1;
11741172
begin
1175-
~SYM[4] <= to_integer(~ARG[6])
1173+
~SYM[4] <= to_integer(~ARG[5])
11761174
-- pragma translate_off
1177-
mod ~LENGTH[~TYP[5]]
1175+
mod ~LENGTH[~TYP[4]]
11781176
-- pragma translate_on
11791177
;
1180-
~SYM[5] <= to_integer(~ARG[8])
1178+
~SYM[5] <= to_integer(~ARG[7])
11811179
-- pragma translate_off
1182-
mod ~LENGTH[~TYP[5]]
1180+
mod ~LENGTH[~TYP[4]]
11831181
-- pragma translate_on
11841182
;
11851183
~IF ~VIVADO ~THEN
1186-
~SYM[6] : process(~ARG[3])
1184+
~SYM[6] : process(~ARG[2])
11871185
begin
1188-
if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
1189-
if ~ARG[7] ~IF ~ISACTIVEENABLE[4] ~THEN and ~ARG[4] ~ELSE ~FI then
1190-
~SYM[2](~SYM[5]) <= ~TOBV[~ARG[9]][~TYP[9]];
1186+
if ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
1187+
if ~ARG[6] ~IF ~ISACTIVEENABLE[3] ~THEN and ~ARG[3] ~ELSE ~FI then
1188+
~SYM[2](~SYM[5]) <= ~TOBV[~ARG[8]][~TYP[8]];
11911189
end if;
11921190
~RESULT <= fromSLV(~SYM[2](~SYM[4]))
11931191
-- pragma translate_off
@@ -1196,11 +1194,11 @@ BlackBox:
11961194
;
11971195
end if;
11981196
end process; ~ELSE
1199-
~SYM[6] : process(~ARG[3])
1197+
~SYM[6] : process(~ARG[2])
12001198
begin
1201-
if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
1202-
if ~ARG[7] ~IF ~ISACTIVEENABLE[4] ~THEN and ~ARG[4] ~ELSE ~FI then
1203-
~SYM[2](~SYM[5]) <= ~ARG[9];
1199+
if ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
1200+
if ~ARG[6] ~IF ~ISACTIVEENABLE[3] ~THEN and ~ARG[3] ~ELSE ~FI then
1201+
~SYM[2](~SYM[5]) <= ~ARG[8];
12041202
end if;
12051203
~RESULT <= ~SYM[2](~SYM[4])
12061204
-- pragma translate_off
@@ -1345,49 +1343,48 @@ BlackBox:
13451343
outputReg: true
13461344
type: |-
13471345
blockRam#
1348-
:: ( KnownDomain dom ARG[0]
1349-
, HasCallStack -- ARG[1]
1350-
, NFDataX a ) -- ARG[2]
1351-
=> Clock dom -- clk, ARG[3]
1352-
=> Enable dom -- en, ARG[4]
1353-
-> Vec n a -- init, ARG[5]
1354-
-> Signal dom Int -- rd, ARG[6]
1355-
-> Signal dom Bool -- wren, ARG[7]
1356-
-> Signal dom Int -- wr, ARG[8]
1357-
-> Signal dom a -- din, ARG[9]
1346+
:: ( HasCallStack -- ARG[0]
1347+
, NFDataX a ) -- ARG[1]
1348+
=> Clock dom -- clk, ARG[2]
1349+
=> Enable dom -- en, ARG[3]
1350+
-> Vec n a -- init, ARG[4]
1351+
-> Signal dom Int -- rd, ARG[5]
1352+
-> Signal dom Bool -- wren, ARG[6]
1353+
-> Signal dom Int -- wr, ARG[7]
1354+
-> Signal dom a -- din, ARG[8]
13581355
-> Signal dom a
13591356
template: |-
13601357
// blockRam begin
1361-
reg ~TYPO ~GENSYM[~RESULT_RAM][1] [0:~LENGTH[~TYP[5]]-1];
1358+
reg ~TYPO ~GENSYM[~RESULT_RAM][1] [0:~LENGTH[~TYP[4]]-1];
13621359
1363-
reg ~TYP[5] ~GENSYM[ram_init][3];
1360+
reg ~TYP[4] ~GENSYM[ram_init][3];
13641361
integer ~GENSYM[i][4];
13651362
initial begin
1366-
~SYM[3] = ~CONST[5];
1367-
for (~SYM[4]=0; ~SYM[4] < ~LENGTH[~TYP[5]]; ~SYM[4] = ~SYM[4] + 1) begin
1368-
~SYM[1][~LENGTH[~TYP[5]]-1-~SYM[4]] = ~SYM[3][~SYM[4]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
1363+
~SYM[3] = ~CONST[4];
1364+
for (~SYM[4]=0; ~SYM[4] < ~LENGTH[~TYP[4]]; ~SYM[4] = ~SYM[4] + 1) begin
1365+
~SYM[1][~LENGTH[~TYP[4]]-1-~SYM[4]] = ~SYM[3][~SYM[4]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
13691366
end
13701367
end
1371-
~IF ~ISACTIVEENABLE[4] ~THEN
1372-
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~GENSYM[~RESULT_blockRam][5]~IF ~VIVADO ~THEN
1373-
if (~ARG[4]) begin
1374-
if (~ARG[7]) begin
1375-
~SYM[1][~ARG[8]] <= ~ARG[9];
1368+
~IF ~ISACTIVEENABLE[3] ~THEN
1369+
always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[2]) begin : ~GENSYM[~RESULT_blockRam][5]~IF ~VIVADO ~THEN
1370+
if (~ARG[3]) begin
1371+
if (~ARG[6]) begin
1372+
~SYM[1][~ARG[7]] <= ~ARG[8];
13761373
end
1377-
~RESULT <= ~SYM[1][~ARG[6]];
1374+
~RESULT <= ~SYM[1][~ARG[5]];
13781375
end~ELSE
1379-
if (~ARG[7] & ~ARG[4]) begin
1380-
~SYM[1][~ARG[8]] <= ~ARG[9];
1376+
if (~ARG[6] & ~ARG[3]) begin
1377+
~SYM[1][~ARG[7]] <= ~ARG[8];
13811378
end
1382-
if (~ARG[4]) begin
1383-
~RESULT <= ~SYM[1][~ARG[6]];
1379+
if (~ARG[3]) begin
1380+
~RESULT <= ~SYM[1][~ARG[5]];
13841381
end~FI
13851382
end~ELSE
1386-
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~SYM[5]
1387-
if (~ARG[7]) begin
1388-
~SYM[1][~ARG[8]] <= ~ARG[9];
1383+
always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[2]) begin : ~SYM[5]
1384+
if (~ARG[6]) begin
1385+
~SYM[1][~ARG[7]] <= ~ARG[8];
13891386
end
1390-
~RESULT <= ~SYM[1][~ARG[6]];
1387+
~RESULT <= ~SYM[1][~ARG[5]];
13911388
end~FI
13921389
// blockRam end
13931390
@
@@ -1413,45 +1410,44 @@ BlackBox:
14131410
kind: Declaration
14141411
type: |-
14151412
blockRam#
1416-
:: ( KnownDomain dom ARG[0]
1417-
, HasCallStack -- ARG[1]
1418-
, NFDataX a ) -- ARG[2]
1419-
=> Clock dom -- clk, ARG[3]
1420-
-> Enable dom -- en, ARG[4]
1421-
-> Vec n a -- init, ARG[5]
1422-
-> Signal dom Int -- rd, ARG[6]
1423-
-> Signal dom Bool -- wren, ARG[7]
1424-
-> Signal dom Int -- wr, ARG[8]
1425-
-> Signal dom a -- din, ARG[9]
1413+
:: ( HasCallStack -- ARG[0]
1414+
, NFDataX a ) -- ARG[1]
1415+
=> Clock dom -- clk, ARG[2]
1416+
-> Enable dom -- en, ARG[3]
1417+
-> Vec n a -- init, ARG[4]
1418+
-> Signal dom Int -- rd, ARG[5]
1419+
-> Signal dom Bool -- wren, ARG[6]
1420+
-> Signal dom Int -- wr, ARG[7]
1421+
-> Signal dom a -- din, ARG[8]
14261422
-> Signal dom a
14271423
template: |-
14281424
// blockRam begin
1429-
~SIGD[~GENSYM[RAM][1]][5];
1430-
logic [~SIZE[~TYP[9]]-1:0] ~GENSYM[~RESULT_q][2];
1425+
~SIGD[~GENSYM[RAM][1]][4];
1426+
logic [~SIZE[~TYP[8]]-1:0] ~GENSYM[~RESULT_q][2];
14311427
initial begin
1432-
~SYM[1] = ~CONST[5];
1433-
end~IF ~ISACTIVEENABLE[4] ~THEN
1434-
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~GENSYM[~COMPNAME_blockRam][3]~IF ~VIVADO ~THEN
1435-
if (~ARG[4]) begin
1436-
if (~ARG[7]) begin
1437-
~SYM[1][~ARG[8]] <= ~TOBV[~ARG[9]][~TYP[9]];
1428+
~SYM[1] = ~CONST[4];
1429+
end~IF ~ISACTIVEENABLE[3] ~THEN
1430+
always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[2]) begin : ~GENSYM[~COMPNAME_blockRam][3]~IF ~VIVADO ~THEN
1431+
if (~ARG[3]) begin
1432+
if (~ARG[6]) begin
1433+
~SYM[1][~ARG[7]] <= ~TOBV[~ARG[8]][~TYP[8]];
14381434
end
1439-
~SYM[2] <= ~SYM[1][~ARG[6]];
1435+
~SYM[2] <= ~SYM[1][~ARG[5]];
14401436
end~ELSE
1441-
if (~ARG[7] & ~ARG[4]) begin
1442-
~SYM[1][~ARG[8]] <= ~TOBV[~ARG[9]][~TYP[9]];
1437+
if (~ARG[6] & ~ARG[3]) begin
1438+
~SYM[1][~ARG[7]] <= ~TOBV[~ARG[8]][~TYP[8]];
14431439
end
1444-
if (~ARG[4]) begin
1445-
~SYM[2] <= ~SYM[1][~ARG[6]];
1440+
if (~ARG[3]) begin
1441+
~SYM[2] <= ~SYM[1][~ARG[5]];
14461442
end~FI
14471443
end~ELSE
1448-
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~SYM[3]
1449-
if (~ARG[7]) begin
1450-
~SYM[1][~ARG[8]] <= ~TOBV[~ARG[9]][~TYP[9]];
1444+
always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[2]) begin : ~SYM[3]
1445+
if (~ARG[6]) begin
1446+
~SYM[1][~ARG[7]] <= ~TOBV[~ARG[8]][~TYP[8]];
14511447
end
1452-
~SYM[2] <= ~SYM[1][~ARG[6]];
1448+
~SYM[2] <= ~SYM[1][~ARG[5]];
14531449
end~FI
1454-
assign ~RESULT = ~FROMBV[~SYM[2]][~TYP[9]];
1450+
assign ~RESULT = ~FROMBV[~SYM[2]][~TYP[8]];
14551451
// blockRam end
14561452
@
14571453
@@ -1561,8 +1557,6 @@ synchronous logic. As a consequence, we see in the type signature of
15611557
__asyncRam__
15621558
:: ( 'Enum' addr
15631559
, 'HasCallStack'
1564-
, 'KnownDomain' wdom
1565-
, 'KnownDomain' rdom
15661560
)
15671561
=> 'Clock' wdom -- ^ 'Clock' to which to synchronize the write port of the RAM
15681562
-> 'Clock' rdom -- ^ 'Clock' to which the read address signal, @r@, is synchronized to
@@ -1675,9 +1669,7 @@ Finally we combine all the components in:
16751669
16761670
@
16771671
asyncFIFOSynchronizer
1678-
:: ( 'KnownDomain' wdom
1679-
, 'KnownDomain' rdom
1680-
, 2 <= addrSize )
1672+
:: ( 2 <= addrSize )
16811673
=> SNat addrSize
16821674
-- ^ Size of the internally used addresses, the FIFO contains @2^addrSize@
16831675
-- elements.
@@ -1796,9 +1788,7 @@ ptrSync clk1 clk2 rst2 en2 =
17961788
17971789
-- Async FIFO synchronizer
17981790
asyncFIFOSynchronizer
1799-
:: ( 'KnownDomain' wdom
1800-
, 'KnownDomain' rdom
1801-
, 2 <= addrSize )
1791+
:: ( 2 <= addrSize )
18021792
=> SNat addrSize
18031793
-- ^ Size of the internally used addresses, the FIFO contains @2^addrSize@
18041794
-- elements.

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